Abstract: A window generating circuit of an image processing apparatus which processes an image is provided. The circuit includes a main controller, a memory device, first, second and third registers, and a window generator. The main controller inputs an original clock signal and generates first and second line memory read control signals, first and second line memory write control signals, a pixel clock, and address signals for first and second line memories based on the original clock signal. The memory device contains the first and second line memories. The first register stores current pixel data in accordance with the pixel clock, and the current pixel data relates to a current line of pixels of the image. The second register stores first line memory data output from the first line memory in accordance with the first line memory read control signal, and the first line memory data relates to a first line of pixels which precedes the current line of pixels.

Abstract: A herb medicine extract-containing non-bleeding striped dentifrice composition, consisting essentially of a striped dentifrice component and a base dentifrice component, each component comprising the following ingredients at the substantially same amount: a. an abrasive that has a BET surface area of 10 m.sup.2 /g or less and an average particle diameter of 1 to 30 .mu.m upon measurement by Coulter Counter method, and shows oil absorption (linseed oil, ml/100 g) of 50 or less; b. a binder selected from the group consisting of xanthan gum, carrageenan, sodium carboxymethylcellulose, and the mixtures thereof; c. an alkyl sulfonate of anionic surfactants; and d. a humectant, and said striped dentifrice component containing herb medicine extracts at an amount of 0.001 to 10% by weight, on the basis of dry solid substance. It is non-bleeding by virtue of the substantially same formulation in the two components and the herb medicine extracts allow the dentifrice composition to suppress the formation of plaque.

Abstract: A leadless alloy for soldering containing 0.1 to 5.0% bismuth, 0.1 to 5.0% silver, 0.1 to 3.0% antimony, 0.1 to 5.5% copper, 0.001 to 0.01% phosphorus, 0.01 to 0.1% germanium and 81.4 to 99.6% tin by weight.

Abstract: A self-bootstrapping device for sufficiently bootstrapping a bias applied to the gate of a MOS transistor included in the decoder of a semiconductor memory device requiring a high integration degree so that the MOS transistor can transmit the potential from its drain to its source. The self-bootstrapping device includes a first NMOS transistor for a signal transmission, and a second NMOS transistor connected between the gate of the first NMOS transistor and an address decoder circuit, the second NMOS transistor being applied at its gate with a source voltage, wherein the second NMOS transistor comprises a first diffusion region formed at a required portion of a semiconductor substrate, a second diffusion region formed around the first diffusion region while being spaced apart from the first diffusion region by a desired distance, and a gate electrode formed on the semiconductor substrate between the first and second diffusion regions.

Abstract: Disclosed is a compact zoom lens system. The lens systems includes a first lens group having positive refractive power; a second lens group having negative refractive power; a third lens group having positive refractive power; and a fourth lens group having positive refractive power. The first lens group and the third lens group are fixed against an image plane. The second lens group is linearly movable for variable magnification. The fourth lens group is able to compensate for moving of an image plane and is linearly movable toward an object for focusing. The lens system is governed by the following relationship: 0<.vertline.f.sub.II-2 /f.sub.II-3 .vertline.<1.2, where f.sub.II-2 is a focal length of a second lens of the second lens group, and f.sub.II-3 is a focal length of a third lens of the second lens group.

Abstract: An improved programmable control sequencer and a method for its map allocation capable of reducing a size of program RAM in a disk controller, of a magnetic disk drive storage system. The programmable control sequencer includes a program random access memory (RAM) having a 16.times.7 bit size of storage area, provided with a branch/data selection field, an encoded next address/count field and an output field. The branch/data selection field has either one of a branch condition or count field enable information and selects a given data register to compare data read out from a disk with data of the selected data register. The encoded next address/count field has an encoded value of either a next address or a count value according to the branch condition. The output field is used for testing a synchronization outside of said programmable control sequencer.

Abstract: A liquid crystal display having a liquid crystal mixture of cholesteric and nematic liquid crystal materials and a method of manufacturing the display. A polymer-liquid crystal mixture, obtained by mixing a mixture of cholesteric and nematic liquid crystals with a polymer compound, is sealed in a plurality of cells between two substrates having respective electrodes. Various mixtures are used in different cells so that different colors can be displayed.

Abstract: An improved programmable control sequencer and a method for its map allocation capable of reducing the size of program RAM used in a disk controller of a magnetic disk drive storage system, thereby efficiently reducing a work load of a microcontroller unit in the disk controller. The map allocation method is performed in a program random access memory having a 32.times.2 byte size of data storage area in the disk controller, the program random access memory being provided with the sequencer map allocation including a branch field, a next address/count field, an output field, a gate field, a field region and a data selection field. The branch field is provided with branch condition or count field enable information. The next address/count field selectively has a next address or a count value according to the branch condition.

Abstract: A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.

Abstract: The present invention relates to a novel mutant of Aspergillus terreus which shows a resistance to both cerulenin and L-methionine analogue, and a process for preparing mevinolinic acid which comprises aerobic culture of the mutant strain and recovery of mevinolinic acid. The mutant of the present invention provides a remarkably high productivity of mevinolinic acid while reducing the production of byproducts such as mevinolinic acid analogues, when compared with a wild type Aspergillus terreus isolated from soil environment in Korea, and it successfully produce mevinolinic acid by employing monosaccharides such as glucose and galactose, unlike the mother strain.

Abstract: A semiconductor memory device having a macro command function includes a macro storage section for storing a series of external instructions synchronized with a clock signal and a plurality of interval data corresponding to a number of clock pulses occurring between the external instructions. A counter is also included for counting the clock pulses and for producing an output representing a number of clock pulses occurring since an initialization of the counter, and a selecting section is included for selecting between a current external instruction synchronized with the clock signal and the external instructions read out from the macro storage section.

Abstract: A multi-port universal asynchronous receiver/transmitter (UART) system is disclosed having time division multiplexing and demultiplexing. The system has plural UART's and includes a time slot generating unit for generating time slot signals corresponding to defined time slots which correspond in number to the plurality of UART's. A receiving data separating unit separates a single stream of received data into a plurality of receiving data streams to correspond with the time slots. Plural receiving data control units time expand respective ones of the separated receiving data streams. The UART's each receive a respective one of the time expanded receiving data streams and output them to an appliance, such as a computer. The UART's also receive data, from the appliance, for transmission. Plural transmitting data control units each receive a stream of transmitting data from a respective one of the plurality of UART's.

Abstract: A method and apparatus of improving user response time during cellular hand-offs and radio frequency changes in a Transmission Control Protocol/Internet Protocol (TCP/IP) mobile environment. In the mobile environment there is at least a mobile end station (20), a mobile data base station (22), a mobile data intermediate system (MDIS) (30) and a fixed end station (40). The MDIS (30) keeps track of the mobile end station (20) as it roams through the mobile environment. As a result, the MDIS (30) can distinguish between delays due to network congestion and delays due to cellular hand-offs. Further, the mobile data base station (22) informs the MDIS (30) of any changes in the radio frequency signal, thus allowing the MDIS (30) to also recognize delays due to changes in the radio frequency signal. With the knowledge of being able to identify the cause of the delays, the MDIS (30) is able to initiate or suppress a congestion control and recovery process.

Abstract: An error-tolerant apparatus and method are disclosed for controlling disk read/write actions on a hard disk drive having no identification (ID) information in the data sectors. A servo sector number is calculated each time a servo sector pulse is input. When a target servo sector number is the same as the calculated servo sector number, a determination is made whether a data read/write error exists. If there is no error, a servo sector is detected and the calculated servo sector number is updated. If there is an error, the calculated servo sector number is maintained. Afterwards, a data read/write error is detected when the target servo sector is detected, the data sector number in the maintained servo sector is set to a number of data sector units to be skipped, and the disk read/write operation is performed from the data sector next to the previous sector.

Abstract: A Viterbi decoder which operates a plurality of states at one time to thereby decode a plurality of channels at an increased speed. The decoder includes a branch metric calculating unit which receives convolutional data and calculates a plurality of branch metrics. A branch metric allocating unit allocates the plurality of branch metrics as even and odd branch metrics. A state metric storing unit stores a current state metric and allocates a plurality of state metrics as even and odd state metrics. First and second add-compare-select (ACS) units perform addition, comparison, and selection on the even branch and state metrics, and select paths having optimum distances. Third and fourth ACS units perform addition, comparison, and selection on the odd branch and state metrics, and select paths having optimum distances. A path tracing logic unit traces the path selection information selected in the first through fourth ACS units, and outputs decoded data.

Abstract: A conductive composition and a CRT bulb employing the conductive layer. The conductive composition includes from about 0.4 to about 10 wt % of tin oxide, from about 4.5 to about 7.0 wt % of a dispersing agent, from about 3.5 to about 7.0 wt % of an antiabsorbent, from about 0.8 to about 4.0 wt % of a vaporization inhibitor, and from about 0.020 to about 0.25 wt % of a surfactant, based on the total weight of an alcoholic solvent. The conductive composition exhibits good solubility, coating performance, and heat stability, and a conductive layer formed of the conductive composition exhibits low surface resistance and enhanced luminance.

Abstract: A polymer for a photo-conductive layer and a preparation method thereof is provided. The polymer is suitable for using as a charge transporting material for a photo-conductive layer owing to its excellent electron transporting capacity as well as high solubility to a solvent and good compatibility with the binder polymer.

Abstract: A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.

Abstract: Methods of forming field oxide isolation regions in a semiconductor substrate include the steps of exposing residual polysilicon defects contained within preliminary field oxide isolation regions and then performing a cleaning step to etch and reduce the size of the exposed defects (or eliminate the defects altogether). The preliminary field oxide isolation regions are then oxidized to preferably convert any remaining polysilicon defects into silicon dioxide and then a final oxide etching step is performed to define the shapes of the final field oxide isolation regions. Preferably, a pad oxide layer is formed on a face of a semiconductor substrate and then a masking layer is formed on the pad oxide layer, opposite the face of the substrate. The masking layer is then patterned to define an opening therein which exposes an upper surface of the pad oxide layer.