Patents by Inventor Woo-Jin Rim
Woo-Jin Rim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10311946Abstract: The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.Type: GrantFiled: July 28, 2016Date of Patent: June 4, 2019Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Han-Wool Jeong, Woo-Jin Rim, Tae-Joong Song, Seong-Ook Jung, Gyu-Hong Kim
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Patent number: 9940998Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.Type: GrantFiled: March 24, 2017Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Hoon Jung, Sung-Hyun Park, Woo-Jin Rim
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Publication number: 20180005692Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary hit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.Type: ApplicationFiled: March 24, 2017Publication date: January 4, 2018Inventors: JONG-HOON JUNG, SUNG-HYUN PARK, WOO-JIN RIM
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Publication number: 20170053696Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.Type: ApplicationFiled: July 28, 2016Publication date: February 23, 2017Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Han-Wool JEONG, Woo-Jin RIM, Tae-Joong SONG, Seong-Ook JUNG, Gyu-Hong KIM
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Patent number: 9571076Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.Type: GrantFiled: October 7, 2015Date of Patent: February 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Woo Seo, Sung-Hyun Park, Woo-Jin Rim, Ha-Young Kim, Jae-Ha Lee, Yong-Ho Kim
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Patent number: 9324384Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.Type: GrantFiled: October 2, 2014Date of Patent: April 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Joong Song, Sung-Hyun Park, Woo-Jin Rim, Gi-Young Yang
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Publication number: 20160105166Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.Type: ApplicationFiled: October 7, 2015Publication date: April 14, 2016Inventors: JAE-WOO SEO, SUNG-HYUN PARK, WOO-JIN RIM, HA-YOUNG KIM, JAE-HA LEE, YONG-HO KIM
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Publication number: 20150206556Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.Type: ApplicationFiled: October 2, 2014Publication date: July 23, 2015Inventors: Tae-Joong SONG, Sung-Hyun PARK, Woo-Jin RIM, Gi-Young YANG
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Patent number: 8854101Abstract: An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit.Type: GrantFiled: February 8, 2013Date of Patent: October 7, 2014Assignee: Korea University Research and Business FoundationInventors: Jong Sun Park, Woo Jin Rim
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Patent number: 8416637Abstract: A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.Type: GrantFiled: July 14, 2010Date of Patent: April 9, 2013Assignee: SK Hynix Inc.Inventor: Woo Jin Rim
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Publication number: 20110157969Abstract: A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.Type: ApplicationFiled: July 14, 2010Publication date: June 30, 2011Applicant: Hynix Semiconductor Inc.Inventor: Woo Jin RIM
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Publication number: 20110058411Abstract: A phase change memory system capable of gradually reducing current at the time of writing set data by using a small number of control circuits while occupying a small dimension is disclosed. The phase change memory system includes a memory cell array including a plurality of memory cells, each including a phase change material which is changed into a set or reset state depending on the amount of current, and a write driver supplying current corresponding to a set or reset state to a selected memory cell of the memory cell array. The write driver includes a slow quenching unit including an analog circuit supplying current slowly decreased in the memory cell array.Type: ApplicationFiled: December 21, 2009Publication date: March 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Woo Jin RIM
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Patent number: 7902872Abstract: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.Type: GrantFiled: August 23, 2007Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Hong Kim, Soo-Won Kim, Gil-Su Kim, Woo-Kwan Lee, Woo-Jin Rim
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Patent number: 7812658Abstract: A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation, tOS = 2 ? ? N × DD = 2 ? ? N × L × tCLK M where each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.Type: GrantFiled: December 30, 2008Date of Patent: October 12, 2010Assignee: Hynix Semiconductor Inc.Inventor: Woo-Jin Rim
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Publication number: 20100052749Abstract: A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation, tOS = 2 ? ? N × DD = 2 ? ? N × L × tCLK M where each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.Type: ApplicationFiled: December 30, 2008Publication date: March 4, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventor: Woo-Jin RIM
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Publication number: 20080048720Abstract: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Inventors: Ki-Hong Kim, Soo-Won Kim, Gil-Su Kim, Woo-Kwan Lee, Woo-Jin Rim