Abstract: The present invention relates to a peptide with anti-inflammatory activity, wherein the peptide comprises any one amino acid sequence of SEQ ID NO: 1 to SEQ ID NO: 161, the peptide has above 80% homology of amino acid sequence with above-mentioned sequences, or the peptide is the fragment of the above-mentioned peptides. The present invention also relates to an inflammatory composition comprising the above mentioned peptides. According to the present invention, a peptide that has at least one amino acid sequence of SEQ ID NO: 1 to SEQ ID NO: 161 has outstanding efficacy in both suppressing inflammation and in prophylactic means. Therefore, the composition comprising the peptides of this invention can be used as anti-inflammatory pharmaceutical compositions or as cosmetic compositions, in turn, treating and preventing a variety of different types of inflammatory diseases.

Abstract: The present invention relates to a peptide with anti-inflammatory activity, wherein the peptide comprises SEQ ID NO: 1, the peptide has above 80% homology of amino acid sequence with above-mentioned sequence, or the peptide is the fragment of the above-mentioned peptides. The present invention also relates to an inflammatory composition comprising the above mentioned peptides. According to the present invention, a peptide comprising a sequence of SEQ ID NO: 1 has an outstanding efficacy in both suppressing inflammation and in prophylactic means. Therefore, the composition comprising the peptide of this invention can be used as anti-inflammatory pharmaceutical composition or as cosmetic composition, in turn, treating and preventing a variety of different types of inflammatory diseases.

Abstract: A multilayer ceramic electronic component includes a ceramic main body including dielectric layers and satisfying T/W>1.0 when W and T are width and thickness, respectively; and first and second internal electrodes stacked in the ceramic main body and facing each other with the dielectric layer interposed therebetween, the ceramic main body including an active layer corresponding to a capacitance forming portion contributing to capacitance formation and a cover layer corresponding to a non-capacitance forming portion provided on at least one of uppermost and lowermost surfaces of the active layer, and when the active layer is divided into three regions in a direction in which the first and second internal electrodes are stacked, an average width of internal electrodes in a central region of the three regions is Wa, and an average width of internal electrodes in upper and lower regions of the three regions is Wb, 0.920?Wb/Wa?0.998 is satisfied.

Abstract: There are provided a multilayer ceramic electronic component and a mounting board therefor, the multilayer ceramic electronic component including a ceramic body having a hexahedral shape, including dielectric layers, and satisfying T/W>1.0 when a length of the ceramic body is defined as L, a width of a lower surface of the ceramic body is defined as W, and a thickness of the ceramic body is defined as T, and first and second internal electrodes stacked in the ceramic body so as to face each other, having the respective dielectric layers interposed therebetween, wherein when a width of an upper surface of the ceramic body is defined as Wa, 0.800?Wa/W?0.985 is satisfied.

Abstract: There are provided a multilayer ceramic electronic component and a mounting board therefor, the multilayer ceramic electronic component including a ceramic body having a hexahedral shape, including dielectric layers, and satisfying T/W>1.0 when a length of the ceramic body is defined as L, a width of a lower surface of the ceramic body is defined as W, and a thickness of the ceramic body is defined as T, and first and second internal electrodes stacked in the ceramic body so as to face each other, having the respective dielectric layers interposed therebetween, wherein when a width of an upper surface of the ceramic body is defined as Wa, 0.800?Wa/W?0.985 is satisfied.

Abstract: A multilayer ceramic electronic component includes a ceramic main body including dielectric layers and satisfying T/W>1.0 when W and T are width and thickness, respectively; and first and second internal electrodes stacked in the ceramic main body and facing each other with the dielectric layer interposed therebetween, the ceramic main body including an active layer corresponding to a capacitance forming portion contributing to capacitance formation and a cover layer corresponding to a non-capacitance forming portion provided on at least one of uppermost and lowermost surfaces of the active layer, and when the active layer is divided into three regions in a direction in which the first and second internal electrodes are stacked, an average width of internal electrodes in a central region of the three regions is Wa, and an average width of internal electrodes in upper and lower regions of the three regions is Wb, 0.920?Wb/Wa?0.998 is satisfied.

Abstract: Disclosed is an AAL2 (ATM (Asynchronous Transfer Mode) Adaptation Layer 2) switching apparatus. A cell deassembler for deassembling a payload of a received ATM cell into a CPS (Common Part Sublayer) packet, and generating a first VPC (Virtual Path Connection) by using the header of the ATM cell. A header converter for receiving the CPS packet from the cell deassembler and converting the first VPC into a second VPC by using a lookup table which have a number of VPCs and CIDs (Channel Identifiers) for changing the VPC. A cell assembler for receiving the CPS packet from the header converter, assembling an ATM cell which have the CPS packet and an ATM header generated from the second VPC.

Abstract: Disclosed is an AAL2 (ATM (Asynchronous Transfer Mode) Adaptation Layer 2) switching apparatus. A cell deassembler for deassembling a payload of a received ATM cell into a CPS (Common Part Sublayer) packet, and generating a first VPC (Virtual Path Connection) by using the header of the ATM cell. A header converter for receiving the CPS packet from the cell deassembler and converting the first VPC into a second VPC by using a lookup table which have a number of VPCs and CIDs (Channel Identifiers) for changing the VPC. A cell assembler for receiving the CPS packet from the header converter, assembling an ATM cell which have the CPS packet and an ATM header generated from the second VPC.