Patents by Inventor Woo June KWON

Woo June KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141332
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Woo June Kwon, Jong Hoon Kim, Chan Sun Hyun
  • Publication number: 20180145087
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Woo June KWON, Jong Hoon KIM, Chan Sun HYUN
  • Patent number: 9911751
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Woo June Kwon, Jong Hoon Kim, Chan Sun Hyun
  • Patent number: 9754962
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: September 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
  • Publication number: 20170179148
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Application
    Filed: May 16, 2016
    Publication date: June 22, 2017
    Inventors: Woo June KWON, Jong Hoon KIM, Chan Sun HYUN
  • Publication number: 20160254272
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON
  • Patent number: 9368511
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
  • Publication number: 20160079275
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON
  • Patent number: 9224751
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
  • Publication number: 20150279856
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Application
    Filed: August 6, 2014
    Publication date: October 1, 2015
    Inventors: Chan Sun HYUN, Myung Kyu AHN, Woo June KWON