Patents by Inventor Woo-Jung Sun

Woo-Jung Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Driving method of nonvolatile memory device using variable resistive element
    Patent number: 9659644
    Abstract: Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoon Jeong, Woo-Jung Sun, Kwang-Jin Lee, Jae-Yun Lee
  • Nonvolatile memory device with reduced coupling noise and driving method thereof
    Patent number: 9570168
    Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yun Lee, Woo-Jung Sun, Kwang-Jin Lee, Dong-Hoon Jeong, Beak-Hyung Cho
  • Nonvolatile Memory Device with Reduced Coupling Noise and Driving Method Thereof
    Publication number: 20160055905
    Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 25, 2016
    Inventors: Jae-Yun Lee, Woo-Jung Sun, Kwang-Jin Lee, Dong-Hoon Jeong, Beak-Hyung Cho
  • DRIVING METHOD OF NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT
    Publication number: 20150221369
    Abstract: Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 6, 2015
    Inventors: DONG-HOON JEONG, WOO-JUNG SUN, KWANG-JIN LEE, JAE-YUN LEE
  • Memory cell array and semiconductor memory device including the same
    Patent number: 7894241
    Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Sang Lee, Woo-Jung Sun, Jung-Bae Lee
  • MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    Publication number: 20090147559
    Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 11, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Sang LEE, Woo-Jung SUN, Jung-Bae LEE