Patents by Inventor Woo-pyo Jeong
Woo-pyo Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230186989Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.Type: ApplicationFiled: May 17, 2022Publication date: June 15, 2023Applicant: SK hynix Inc.Inventors: Jung Shik JANG, In Su PARK, Woo Pyo JEONG, Jung Dal CHOI, Jae Woong KIM, Jeong Hwan KIM
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Patent number: 10324629Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.Type: GrantFiled: January 12, 2018Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Lee, Eun-Suk Cho, Woo-Pyo Jeong, Sang-Wan Nam, Jung-Ho Song, Yun-Ho Hong, Jae-Hoon Lee
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Publication number: 20180292989Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.Type: ApplicationFiled: January 12, 2018Publication date: October 11, 2018Inventors: JONG-HOON LEE, EUN-SUK CHO, WOO-PYO JEONG, SANG-WAN NAM, JUNG-HO SONG, YUN-HO HONG, JAE-HOON LEE
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Patent number: 8675436Abstract: A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current.Type: GrantFiled: June 29, 2010Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Young Kim, Woo-Pyo Jeong
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Patent number: 8315118Abstract: A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.Type: GrantFiled: April 27, 2010Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Gyu Chu, Woo-Pyo Jeong
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Patent number: 8202764Abstract: Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.Type: GrantFiled: February 9, 2009Date of Patent: June 19, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Woo-Pyo Jeong
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Publication number: 20110007594Abstract: A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current.Type: ApplicationFiled: June 29, 2010Publication date: January 13, 2011Inventors: Ho-Young Kim, Woo-Pyo Jeong
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Publication number: 20110008932Abstract: Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.Type: ApplicationFiled: August 10, 2010Publication date: January 13, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Woo-Pyo Jeong
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Publication number: 20100271892Abstract: A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.Type: ApplicationFiled: April 27, 2010Publication date: October 28, 2010Inventors: YONG-GYU CHU, Woo-Pyo Jeong
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Patent number: 7623408Abstract: A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.Type: GrantFiled: April 3, 2007Date of Patent: November 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Woo-Pyo Jeong
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Publication number: 20090209061Abstract: Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.Type: ApplicationFiled: February 9, 2009Publication date: August 20, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Woo-Pyo Jeong
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Patent number: 7532535Abstract: A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.Type: GrantFiled: July 6, 2006Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Woo-Pyo Jeong
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Patent number: 7532538Abstract: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.Type: GrantFiled: December 6, 2006Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seouk-Kyu Choi, Woo-Pyo Jeong
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Publication number: 20080049540Abstract: A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.Type: ApplicationFiled: April 3, 2007Publication date: February 28, 2008Inventor: Woo-Pyo Jeong
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Publication number: 20070183229Abstract: A Multi Chip Package (MCP) and a related method for enabling a cell in the MCP are provided. In one embodiment, the MCP comprises a first memory device and a second memory device storing repair address information about the first memory device.Type: ApplicationFiled: January 19, 2007Publication date: August 9, 2007Inventors: Seouk-Kyu Choi, Woo-Pyo Jeong
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Publication number: 20070165475Abstract: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.Type: ApplicationFiled: December 6, 2006Publication date: July 19, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seouk-Kyu CHOI, Woo-Pyo JEONG
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Publication number: 20070014177Abstract: A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.Type: ApplicationFiled: July 6, 2006Publication date: January 18, 2007Inventor: Woo-Pyo Jeong
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Patent number: 6188631Abstract: A column select circuit capable of minimizing load to data input/output lines, a semiconductor memory device having the same, and an arrangement method for the semiconductor memory device are described. In the semiconductor memory device having column select circuits, each column select circuit selects one of at least two banks in a memory block and selects a predetermined bit line among a plurality of bit lines in the selected bank to transfer data of the selected bit line to data input/output line. The column select circuit includes one or more first select portions for connecting the bit lines of the selected bank to the corresponding first data lines in response to a bank select signal to select a predetermined bank. One or more second select portions connects the first data lines to a second data line in response to each column select signal which represents the address of each bit line.Type: GrantFiled: February 7, 2000Date of Patent: February 13, 2001Assignee: Samsung Electronics Co., LTDInventors: Jung-bae Lee, Woo-pyo Jeong