Abstract: A semiconductor fabrication technique for forming a ferroelectric capacitor, in which the thermal burden is reduced by using an SBT-based ferroelectric thin film such as SrxBiyTa2O9 (‘SBT’) or SrxBiy(TaiNbj)2O9 (‘SBT(N)’) as the dielectric medium. The method includes the following steps. A strontium-bismuth-tantalum oxide film is formed on a semiconductor substrate, with a conductive film for a lower electrode having been formed on the semiconductor substrate (first step). An NH3 gas is flowed at a stabilizing step of a rapid thermal annealing so as to reduce organic materials bonded with metal elements of the strontium-bismuth-tantalum oxide film (second step). An oxide gas is flowed at a temperature of 450˜650° C. at an annealing step of the rapid thermal annealing so as to induce a perovskite nuclear formation in the strontium-bismuth-tantalum oxide film (third step).

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device which includes the steps of preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; forming a first conductive layer and then a dielectric layer on the active matrix; carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; forming a second conductive on top of the dielectric layer; carrying out a thermal annealing in a furnace; forming a capacitor structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; carrying out a first recovery; forming a third insulating layer on the capacitor structure and the second insulating layer; patterning the third insulating layer to form a first opening and a second opening; and carrying out a second recover

Abstract: A method for manufacturing a ferroelectric memory device including the steps of forming a polysilicon plug to connect a transistor through an interlayer dielectric (ILD) layer which is formed on a semiconductor substrate incorporating the transistor therein, forming a first conductive layer on the polysilicon plug and the ILD layer, forming a ferroelectric layer on the first conductive layer, carrying out a heat treatment for crystallization of the ferroelectric layer in a presence of an inert gas, forming a second conductive layer on the ferroelectric layer, and patterning the second conductive layer, the ferroelectric layer and the first conductive layer to form a ferroelectric capacitor.

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device which includes the steps of preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; forming a first conductive layer and then a dielectric layer on the active matrix; carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; forming a second conductive on top of the dielectric layer; carrying out a thermal annealing in a furnace; forming a capacitor structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; carrying out a first recovery; forming a third insulating layer on the capacitor structure and the second insulating layer; patterning the third insulating layer to form a first opening and a second opening; and carrying out a second recover

Abstract: A method for fabricating a ferroelectric capacitor in a ferroelectric memory device includes the steps of forming a first conductive layer on a semiconductor structure prepared for a formation of ferroelectric capacitor, forming a first ferroelectric layer on said first conductive layer, carrying out a rapid thermal annealing for nucleation in said ferroelectric layer, forming a second conductive layer on said ferroelectric layer, and carrying out a thermal treatment for a grain growth in said ferroelectric layer, thereby the interface characteristics are improved, reducing leakage currents and preventing a peeling phenomenon during a following etching process.