Abstract: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.

Abstract: A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

Abstract: An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.

Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.

Abstract: A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.

Abstract: A power supply device in a semiconductor memory includes a power control means and a power generation means. The power control means divides a self-refresh section into an active-precharge mode and an idle mode depending on an operation characteristic of the semiconductor memory, and generates a control signal for controlling power strength applied to the semiconductor memory during operation in each mode. The power generation mode generates a different power level in response to a power control signal from the power control means to provide to the semiconductor memory. Meanwhile, the power supply device according to the present invention provides relatively strong power to the semiconductor memory a predetermined time period in advance of the active-precharge mode.

Abstract: A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

Abstract: An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.

Abstract: A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

Abstract: A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.

Abstract: Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.