Patents by Inventor Woo Sig Min

Woo Sig Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10395972
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 27, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
  • Publication number: 20180166322
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Application
    Filed: January 16, 2018
    Publication date: June 14, 2018
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Da Soon LEE, Hyung Suk CHOI, Jeong Gyu PARK, Gil Ho LEE, Hyun Tae JUNG, Meng An JUNG, Woo Sig MIN, Pil Seung KANG
  • Patent number: 9922865
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: March 20, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
  • Publication number: 20140291767
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Application
    Filed: October 30, 2013
    Publication date: October 2, 2014
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
  • Patent number: 8410528
    Abstract: Disclosed is a CMOS image sensor, which can minimize a reflectance of light at an interface between a photodiode and an insulating film, thereby enhancing image sensitivity. Such a CMOS image sensor includes a substrate provided with a photodiode consisting of Si, an insulating film consisting of SiO2 and formed on the substrate, a semi-reflection film interposed between the substrate and the insulating film, and metal interconnections, color filters and micro lenses constituting individual unit pixels. The semi-reflection film has a refraction index value between those of the Si photodiode and the SiO2 insulating film.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 2, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Woo Sig Min
  • Patent number: 7772664
    Abstract: Disclosed is a CMOS image sensor, which can minimize a reflectance of light at an interface between a photodiode and an insulating film, thereby enhancing image sensitivity. Such a CMOS image sensor includes a substrate provided with a photodiode consisting of Si, an insulating film consisting of SiO2 and formed on the substrate, an anti-reflection film interposed between the substrate and the insulating film, and metal interconnections, color filters and micro lenses constituting individual unit pixels. The semi-reflection film has a refraction index value between those of the Si photodiode and the SiO2 insulating film.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: August 10, 2010
    Inventor: Woo Sig Min
  • Publication number: 20100193892
    Abstract: Disclosed is a CMOS image sensor, which can minimize a reflectance of light at an interface between a photodiode and an insulating film, thereby enhancing image sensitivity. Such a CMOS image sensor includes a substrate provided with a photodiode consisting of Si, an insulating film consisting of SiO2 and formed on the substrate, a semi-reflection film interposed between the substrate and the insulating film, and metal interconnections, color filters and micro lenses constituting individual unit pixels. The semi-reflection film has a refraction index value between those of the Si photodiode and the SiO2 insulating film.
    Type: Application
    Filed: April 8, 2010
    Publication date: August 5, 2010
    Inventor: Woo Sig Min
  • Patent number: 7041582
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. A barrier metal layer for blocking a metal material from being diffused into an insulating film is formed by means of an ALD method. At this time, the barrier metal layer is formed to have an amorphous structure and the barrier metal layer at the bottom of a contact hole or a via hole is selectively removed so that the barrier metal layer having good anti-diffusion properties even in a thin thickness is obtained. Therefore, it is possible to prevent resistance from increasing due to the barrier metal layer.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: May 9, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Sig Min
  • Publication number: 20020187624
    Abstract: A method for forming a metal line of a semiconductor device is disclosed, which improves a crystal structure of a Cu line 111 to improve electro-migration characteristics and reliability. The method includes forming a trench on a substrate by patterning an insulating interlayer. A barrier metal film is formed on the trench and the insulating interlayer. A seed Cu film is formed on the barrier metal film. A PVD metal film is formed on the seed Cu film by a physical vapor deposition (PVD) process. An electroplated metal film is deposited on the PVD metal film to fill the trench. Lastly, a metal line is formed in the trench by removing the films to expose the insulating interlayer on either side of the metal line in the trench.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 12, 2002
    Inventor: Woo Sig Min