Abstract: A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.

Abstract: An apparatus for manufacturing a semiconductor device includes a substrate transfer unit configured to transfer a substrate, a rail unit including a driving rail extending in a first direction that the substrate transfer unit moves and a stopper on a side of the driving rail in a second direction crossing the first direction, and a lifting unit configured to move in the first direction and a third direction perpendicular to the first and second directions to remove the substrate transfer unit from the rail unit, wherein the lifting unit is configured to contact the stopper to move the stopper from a closed state to an open state.

Abstract: An exemplary embodiment of the present invention provides a urea water manufacturing device which can reduce the time for producing urea water by forming a vibrating atmosphere using an ultrasonic wave generator when stirring urea and pure water supplied inside a stirring tank, and can produce urea water with high purity by real-time feedback control of specific gravity of urea water, and a method thereof. The urea water manufacturing device according to an exemplary embodiment of the present invention includes a pure water supply unit, a urea supply unit, a stirring unit, a specific gravity detection unit, a control unit, and a urea water discharge unit.

Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.

Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.

Abstract: A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.

Abstract: A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.

Abstract: A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.

Abstract: A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.

Abstract: The present invention relates to a composition for the treatment of gout, comprising an Angelica gigas Nakai extract which inhibits xanthine oxidase to reduce uric acid in the blood or urine, thereby being effective in the treatment of gout. Further, the present invention relates to a composition for the prevention of inflammation in gout, comprising an Angelica gigas Nakai extract which has an inhibitory effect on the inflammation-inducing enzyme Cox-2. The Angelica gigas Nakai extract of the present invention is a liquid concentrate consisting of 98% by weight or more of decursin and decursinol angelate as main ingredients, and for administration to human, it is extracted with water and ethanol only as an extraction solvent. In addition, a purification method using a difference in temperature and solubility is used, in order to increase its purity.

Abstract: Disclosed herein are a process for the refinement of nitrogen trifluoride gas and an adsorbent used therein. A nitrogen trifluoride (NF3) gas including carbon tetrafluoride (CF4) as an impurity is permeated into a bed of the zeolite 3 A, 4A or 5 A which is ion exchanged with alkali earth metal and is thermally treated at 150 to 600° C. for 0.5 to 100 hours so as to selectively adsorb nitrogen trifluoride onto the bed, followed by the desorption of the nitrogen trifluoride therefrom.

Abstract: Disclosed herein are a process for the refinement of nitrogen trifluoride gas and an adsorbent therefor. A nitrogen trifluoride (NF3) gas including carbon tetrafluoride (CF4) as an impurity is permeated into a bed of zeolite 3A, 4A or 5A which undergoes ion exchange and impregnation with alkali earth metal and is thermally treated at 150 to 600° C. for 0.5 to 100 hours so as to be able to selectively adsorb nitrogen trifluoride onto the bed, followed by the desorption of the nitrogen trifluoride therefrom.

Abstract: Disclosed herein are a process for the refinement of nitrogen trifluoride gas and an adsorbent therefor. A nitrogen trifluoride (NF3) gas including carbon tetrafluoride (CF4) as an impurity is permeated into a bed of zeolite 3 A, 4A or 5 A which undergoes ion exchange and impregnation with alkali earth metal and is thermally treated at 150 to 600° C. for 0.5 to 100 hours so as to be able to selectively adsorb nitrogen trifluoride onto the bed, followed by the desorption of the nitrogen trifluoride therefrom.