Patents by Inventor Woo-Sik Nam

Woo-Sik Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9755169
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: first and second electrodes spaced from each other; at least one nano crystal layer disposed between the first and second electrodes; and first and second material layers respectively disposed between the first and second electrodes and the nano crystal layer and having a bistable conductive property, wherein the first and second material layers are formed asymmetrical to each other.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 5, 2017
    Assignee: IUCF-HYU
    Inventors: Jea Gun Park, Sung Ho Seo, Woo Sik Nam, Jong Sun Lee
  • Publication number: 20150214497
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: first and second electrodes spaced from each other; at least one nano crystal layer disposed between the first and second electrodes; and first and second material layers respectively disposed between the first and second electrodes and the nano crystal layer and having a bistable conductive property, wherein the first and second material layers are formed asymmetrical to each other.
    Type: Application
    Filed: July 27, 2012
    Publication date: July 30, 2015
    Applicant: IUCF-HYU
    Inventors: Jea Gun Park, Sung Ho Seo, Woo Sik Nam, Jong Sun Lee
  • Patent number: 8441472
    Abstract: Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: May 14, 2013
    Assignee: Industry-University Corporation Foundation Hanyang University
    Inventors: Jae-Gun Park, Gon-Sub Lee, Su-Hwan Lee, Sung-Ho Seo, Woo-Sik Nam, Dong-Won Shin, Dal-Ho Kim, Hyun-Min Seung, Jong-Dae Lee
  • Patent number: 8315080
    Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer. The charge trapping layer comprise a nanocrystal layer intervened in an organic layer, and the nanocrystal layer comprises a plurality of nanocrystals.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 20, 2012
    Assignee: IUCF-HYU
    Inventors: Jea Gun Park, Gon Sub Lee, Su Hwan Lee, Dal Ho Kim, Sung Ho Seo, Woo Sik Nam, Hyun Min Seung, Jong Dae Lee, Dong Won Shin
  • Patent number: 8233313
    Abstract: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: July 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jea-Gun Park, Sung-Ho Seo, Woo-Sik Nam, Young-Hwan Oh, Yool-Guk Kim, Hyun-Min Seung, Jong-Dae Lee
  • Publication number: 20120044767
    Abstract: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jae-Gun PARK, Sung-Ho SEO, Woo-Sik NAM, Young-Hwan OH, Yool-Guk KIM, Hyun-Min SEUNG, Jong-Dae LEE
  • Patent number: 8050081
    Abstract: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jea-Gun Park, Sung-Ho Seo, Woo-Sik Nam, Young-Hwan Oh, Yool-Guk Kim, Hyun-Min Seung, Jong-Dae Lee
  • Publication number: 20100208507
    Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.
    Type: Application
    Filed: April 23, 2008
    Publication date: August 19, 2010
    Applicant: IUCF-HYU
    Inventors: Jea Gun Park, Gon Sub Lee, Su Hwan Lee, Dal Ho Kim, Sung Ho Seo, Woo Sik Nam, Hyun Min Seung, Jong Dae Lee, Dong Won Shin
  • Publication number: 20090040805
    Abstract: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.
    Type: Application
    Filed: April 23, 2008
    Publication date: February 12, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jea-Gun Park, Sung-Ho Seo, Woo-Sik Nam, Young-Hwan Oh, Yool-Guk Kim, Hyun-Min Seung, Jong-Dae Lee