Patents by Inventor Woo-Song Ahn
Woo-Song Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11257710Abstract: A method comprises: disposing an ashing resistive layer over a multi-layered mask; sequentially disposing a first and second dummy layer on the ashing resistive layer; sequentially forming a first pattern structure and a second pattern structure there-over over the second dummy layer; recessing the second dummy layer, through the first and the second pattern structure, to partially expose the first dummy layer and to form a target pattern structure defining a target pattern; performing an anisotropic etching process, through the target pattern structure, to recess the exposed portions of the first dummy layer such that the target pattern is transferred to the recessed first dummy layer; performing an ashing process to remove the target pattern structure; and performing a pattern transferring process by recessing the ashing resistive layer and the multi-layered mask through the recessed first dummy layer to transfer the target pattern to the multi-layered mask.Type: GrantFiled: January 10, 2020Date of Patent: February 22, 2022Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventors: Woo-Song Ahn, Yongchul Oh
-
Patent number: 11245019Abstract: A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.Type: GrantFiled: January 10, 2020Date of Patent: February 8, 2022Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventors: Woo-Song Ahn, Sang-Don Yi, Yongchul Oh
-
Publication number: 20210217657Abstract: A method comprises: disposing an ashing resistive layer over a multi-layered mask; sequentially disposing a first and second dummy layer on the ashing resistive layer; sequentially forming a first pattern structure and a second pattern structure there-over over the second dummy layer; recessing the second dummy layer, through the first and the second pattern structure, to partially expose the first dummy layer and to form a target pattern structure defining a target pattern; performing an anisotropic etching process, through the target pattern structure, to recess the exposed portions of the first dummy layer such that the target pattern is transferred to the recessed first dummy layer; performing an ashing process to remove the target pattern structure; and performing a pattern transferring process by recessing the ashing resistive layer and the multi-layered mask through the recessed first dummy layer to transfer the target pattern to the multi-layered mask.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: WOO-SONG AHN, YONGCHUL OH
-
Publication number: 20210217867Abstract: A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: WOO-SONG AHN, SANG-DON YI, YONGCHUL OH
-
Patent number: 10784266Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.Type: GrantFiled: November 6, 2018Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-oh Kim, Ki-seok Lee, Chan-sic Yoon, Je-min Park, Woo-song Ahn
-
Publication number: 20190355728Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.Type: ApplicationFiled: November 6, 2018Publication date: November 21, 2019Inventors: Dong-oh Kim, Ki-seok Lee, Chan-sic Yoon, Je-min Park, Woo-song Ahn
-
Patent number: 10199379Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: December 7, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
-
Publication number: 20180108662Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: ApplicationFiled: December 7, 2017Publication date: April 19, 2018Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
-
Patent number: 9853031Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: February 15, 2017Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
-
Patent number: 8704228Abstract: An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.Type: GrantFiled: December 16, 2011Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-song Ahn, Satoru Yamada, Young-jin Choi
-
Patent number: 8653622Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.Type: GrantFiled: March 1, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Song Ahn, Satoru Yamada, Young-Jin Choi, Seung-Uk Han, Kyo-Suk Chae
-
Publication number: 20120153404Abstract: An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.Type: ApplicationFiled: December 16, 2011Publication date: June 21, 2012Inventors: Woo-song AHN, Satoru YAMADA, Young-Jin Choi
-
Publication number: 20110241099Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.Type: ApplicationFiled: March 1, 2011Publication date: October 6, 2011Inventors: Woo-Song Ahn, Satoru Yamada, Young-Jin Choi, Seung-Uk Han, Kyo-Suk Chae