Abstract: A semiconductor device includes an active region defined by an element isolation region in a base substrate, source and drain regions of a first conductivity type spaced apart from each other, and formed in the active region, a body region of a second conductivity type surrounding the source region, and formed in the base substrate, a drift region of the first conductivity type surrounding the drain region, having a lower impurity concentration than the drain region, and formed in the base substrate, an insulating structure including a buried insulating pattern and a semiconductor pattern sequentially stacked on the drift region, a gate dielectric film including a first portion extending along an upper surface of the body region and a second portion extending along a side surface and an upper surface of the insulating structure, and a gate electrode extending along an upper surface of the gate dielectric film.

Abstract: A semiconductor device includes an active region defined by an element isolation region in a base substrate, source and drain regions of a first conductivity type spaced apart from each other, and formed in the active region, a body region of a second conductivity type surrounding the source region, and formed in the base substrate, a drift region of the first conductivity type surrounding the drain region, having a lower impurity concentration than the drain region, and formed in the base substrate, an insulating structure including a buried insulating pattern and a semiconductor pattern sequentially stacked on the drift region, a gate dielectric film including a first portion extending along an upper surface of the body region and a second portion extending along a side surface and an upper surface of the insulating structure, and a gate electrode extending along an upper surface of the gate dielectric film.

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

Abstract: A semiconductor device includes a substrate having a first conductive type active region, a second conductive type drift region in the active region, a gate covering the active region on the drift region, a gate insulating film disposed between the active region and the gate, a second conductive type drain region in a location spaced apart from the gate in the drift region and having a higher doping concentration than that of the drift region, a first conductive type shallow well region spaced apart from the drain region in the drift region and between the gate and the drain region, and a second conductive type source region formed in the first conductive type shallow well region between the gate and the drain region and having a higher doping concentration than that of the first conductive type shallow well region.