Abstract: A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not overlap with a junction region. A step difference is formed in a storage node junction region, and thus a contact area between a storage node contact and the storage node junction region is increased, resulting in the improvement of operational characteristics of the semiconductor device.

Abstract: A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not overlap with a junction region. A step difference is formed in a storage node junction region, and thus a contact area between a storage node contact and the storage node junction region is increased, resulting in the improvement of operational characteristics of the semiconductor device.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

Abstract: A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period.

Abstract: The semiconductor device includes a plurality of pillar patterns formed over a semiconductor substrate. Each pillar pattern includes a silicon layer; a bit line junction region formed at the bottom of one side of the pillar pattern, and configured to be in contact the silicon layer; a bit line provided between the pillar patterns, coupled to the bit line junction region, and extending along a first direction; and a gate spaced apart from an upper part of the bit line, extending along a second direction perpendicular to the bit line, and formed at a sidewall of the pillar pattern.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which form a bit line only at one side of a line pattern by partially etching a semiconductor substrate in a vertical gate structure, such that a body tied structure for reducing the floating body effect can be implemented. A semiconductor device includes a line pattern formed over a semiconductor substrate, a bit line buried in a bottom part of one side of the line pattern, and a gate formed over the bit line, and located perpendicular to the bit line.

Abstract: A semiconductor device is fabricated by forming a semiconductor substrate as a convex shape to increase a effective channel of a transistor and by stacking a first silicon germanium layer and a first silicon layer on the semiconductor substrate to form a first layer and stacking a second silicon germanium layer and a second silicon layer on the first layer to form a second layer such that the current reduced due to the increased effective channel is ensured, thereby being capable of high speed performance.

Abstract: A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

Abstract: Provided are an electrode device and an apparatus for generating plasma.

Abstract: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an upper portion of the silicon fin, a channel region disposed in a sidewall of the silicon fin between the source region and the drain region, a gate oxide film disposed in a surface of the semiconductor substrate and the sidewall of the silicon fin, and a pair of gate electrodes disposed on the gate oxide films.

Abstract: Provided are an electrode device and an apparatus for generating plasma.

Abstract: A semiconductor device is fabricated by forming a semiconductor substrate as a convex shape to increase a effective channel of a transistor and by stacking a first silicon germanium layer and a first silicon layer on the semiconductor substrate to form a first layer and stacking a second silicon germanium layer and a second silicon layer on the first layer to form a second layer such that the current reduced due to the increased effective channel is ensured, thereby being capable of high speed performance.

Abstract: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.

Abstract: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an upper portion of the silicon fin, a channel region disposed in a sidewall of the silicon fin between the source region and the drain region, a gate oxide film disposed in a surface of the semiconductor substrate and the sidewall of the silicon fin, and a pair of gate electrodes disposed on the gate oxide films.

Abstract: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an upper portion of the silicon fin, a channel region disposed in a sidewall of the silicon fin between the source region and the drain region, a gate oxide film disposed in a surface of the semiconductor substrate and the sidewall of the silicon fin, and a pair of gate electrodes disposed on the gate oxide films.

Abstract: A method for manufacturing a transistor of a semiconductor device is provided. The method includes the steps of: forming a gate over a semiconductor substrate including an NMOS transistor region and a PMOS transistor region; forming a photoresist pattern to open the gate of the PMOS transistor region; forming a first Lightly Doped Drain (LDD) region in the semiconductor substrate on both sides of the gate of the PMOS transistor region; forming a second LDD region in the semiconductor substrate on both sides of the gate of the PMOS transistor region; forming a gate spacer at sidewalls of the gate; and forming a junction region in the semiconductor substrate on the both sides of the gate spacer.

Abstract: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.