Abstract: An automated driving system of a vehicle includes a driver monitoring unit configured to perform at least one of monitoring a gaze of a driver and determining a position of a hand of the driver, an automated-driving-level switching unit configured to determine whether a transition of a driving control over the vehicle is required based on whether driving environment of the vehicle has changed during the vehicle being driven under control of the automated driving system, and determine an automated driving level to be switched based on a driver monitoring result obtained by the drive monitoring unit, and an automated driving control unit configured to control the vehicle according to the automated driving level.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

Abstract: A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to generate a result indicative of whether a number of free memory blocks satisfies a reference after beginning of garbage collection for the memory device, selectively perform a journaling operation for a request based on the result, and program data, collected by the garbage collection, in the memory device.

Abstract: A memory system which stores a journal including mapping change information, either in a first memory area or a second memory area, depending on available space of a memory device included in the memory system, being greater than a threshold.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a SPO detector configured to output a detection signal when a SPO is detected, a memory buffer configured to store host data, and a power loss controller configured to, based on the detection signal, receive dump data corresponding to the host data, store the dump data and a dump age corresponding to the dump data, and output the dump data and the dump age to a memory device, wherein the dump age indicates a number of times that different items of host data have been dumped from the memory buffer to the power loss controller, and the power loss controller is configured to control a recovery operation corresponding to the SPO based on the dump age being received from the memory device.

Abstract: There are provided a memory controller and an operating method thereof. The memory controller includes: a meta data storage for storing meta data including mapping information of data stored in a memory device and valid data information representing whether the data stored in the memory device is valid data; and a migration controller for controlling the memory device to perform a migration operation of moving, to a target memory block, valid data stored in a plurality of source memory blocks included in the memory device, based on the meta data. The migration controller controls the memory device to read a second valid data stored in the second die before reading a first valid data stored in the first die, based on a comparison result between a reference time and a delay time required until before the first valid data is read.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store, in a first memory area or a second memory area each including at least one of the plurality of memory blocks, a journal including mapping change information between a logical address and a physical address according to a number of free memory blocks among the plurality of memory blocks.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to generate a result indicative of whether a number of free memory blocks satisfies a reference after beginning of garbage collection for the memory device, selectively perform a journaling operation for a request based on the result, and program data, collected by the garbage collection, in the memory device.

Abstract: A memory controller includes a first flash translation layer (FTL) generating a physical address corresponding to a first type logical address received from a host on the basis of information about the first memory blocks, a second FTL generating a physical address corresponding to a second type logical address received from the host on the basis of information about the second memory blocks, and a memory control unit controlling the first memory area or the second memory area to perform an operation on the physical address corresponding to the first type logical address or the physical address corresponding to the second type logical address, wherein the first FTL provides the second FTL with block request information for requesting use of the second memory blocks, and generates the physical address corresponding to the first type logical address received from the host on the basis of block allocation information provided by the second FTL.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a SPO detector configured to output a detection signal when a SPO is detected, a memory buffer configured to store host data, and a power loss controller configured to, based on the detection signal, receive dump data corresponding to the host data, store the dump data and a dump age corresponding to the dump data, and output the dump data and the dump age to a memory device, wherein the dump age indicates a number of times that different items of host data have been dumped from the memory buffer to the power loss controller, and the power loss controller is configured to control a recovery operation corresponding to the SPO based on the dump age being received from the memory device.

Abstract: There are provided a memory controller and an operating method thereof. The memory controller includes: a meta data storage for storing meta data including mapping information of data stored in a memory device and valid data information representing whether the data stored in the memory device is valid data; and a migration controller for controlling the memory device to perform a migration operation of moving, to a target memory block, valid data stored in a plurality of source memory blocks included in the memory device, based on the meta data. The migration controller controls the memory device to read a second valid data stored in the second die before reading a first valid data stored in the first die, based on a comparison result between a reference time and a delay time required until before the first valid data is read.

Abstract: A memory controller includes a first flash translation layer (FTL) generating a physical address corresponding to a first type logical address received from a host on the basis of information about the first memory blocks, a second FTL generating a physical address corresponding to a second type logical address received from the host on the basis of information about the second memory blocks, and a memory control unit controlling the first memory area or the second memory area to perform an operation on the physical address corresponding to the first type logical address or the physical address corresponding to the second type logical address, wherein the first FTL provides the second FTL with block request information for requesting use of the second memory blocks, and generates the physical address corresponding to the first type logical address received from the host on the basis of block allocation information provided by the second FTL.

Abstract: The present invention relates to a method for preparing a lithium metal phosphor oxide, the method including: mixing an iron salt solution and a phosphate solution in a reactor; applying a shearing force to the mixed solution in the reactor during the mixing to form a suspension containing nano-sized iron phosphate precipitate particles; obtaining the nano-sized iron phosphate particles from the suspension; and mixing the iron phosphate with a lithium raw material and performing firing, and the lithium metal phosphor oxide according to the present invention has an Equation of LiMnFePO4. Herein, M is selected from the group consisting of Ni, Co, Mn, Cr, Zr, Nb, Cu, V, Ti, Zn, Al, Ga, and Mg, and n is in a range of 0 to 1.

Abstract: A storage device, a storage system comprising the same, and operating methods of the storage device are provided. The storage device includes a first nonvolatile memory cell array which includes a plurality of cell strings arranged in a direction perpendicular to a substrate, and stores first data at a first address, a second nonvolatile memory cell array which stores second data selected from the first data at a second address, in accordance with an access pattern to the first data, and a memory controller which manages a first mapping table indicating that the second data is stored at the second address of the second nonvolatile memory cell array, and a second mapping table indicating that the first data as original data of the second data is stored at the first address.

Abstract: A storage device, a storage system comprising the same, and operating methods of the storage device are provided. The storage device includes a first nonvolatile memory cell array which includes a plurality of cell strings arranged in a direction perpendicular to a substrate, and stores first data at a first address, a second nonvolatile memory cell array which stores second data selected from the first data at a second address, in accordance with an access pattern to the first data, and a memory controller which manages a first mapping table indicating that the second data is stored at the second address of the second nonvolatile memory cell array, and a second mapping table indicating that the first data as original data of the second data is stored at the first address.

Abstract: A thin film transistor includes a gate electrode, a semiconductor overlapping the gate electrode, a gate insulator between the gate electrode and the semiconductor, and a source electrode and a drain electrode electrically connected to the semiconductor, wherein the gate insulator includes an inorganic insulation layer facing the gate electrode and an organic insulation layer facing the semiconductor. A method of manufacturing the thin film transistor and an electronic device including the thin film transistor are provided.

Abstract: A thin film transistor includes a gate electrode, a semiconductor overlapping the gate electrode, a gate insulator between the gate electrode and the semiconductor, and a source electrode and a drain electrode electrically connected to the semiconductor, wherein the gate insulator includes an inorganic insulation layer facing the gate electrode and an organic insulation layer facing the semiconductor. A method of manufacturing the thin film transistor and an electronic device including the thin film transistor are provided.

Abstract: Disclosed is a method for manufacturing a lithium transition metal phosphate. The disclosed method for manufacturing a lithium transition metal phosphate comprises the steps of: injecting reaction materials containing lithium, a transition metal, and a phosphate, into a reactor, and mixing the raw materials at the molecular level in the reactor; and allowing the reaction materials to chemically react in the reactor so as to cause nucleation.