Abstract: This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are subject to higher rates of manufacturing defects and soft errors. Correction of manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.

Abstract: This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are subject to higher rates of manufacturing defects and soft errors. Correction of manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.

Abstract: Sensor elements each of which occupies one of at least two states at a given time, are exposed to an external influence capable of switching a state of at least a random one of the elements. After the exposing has occurred, information identifying the sensor elements, the states of which have been switched, is used to generate random numbers.

Abstract: The present invention relates to a picture display using CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a CMOS image sensor having a testing circuit embedded therein and a method for verifying operation of the CMOS image sensor using the testing circuit. The CMOS image sensor according to the present invention includes a control/interface unit for controlling its operation sensor using a state machine and for interfacing the CMOS image sensor with an external system; a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light; a converter for converting the analogue signals into digital signals to be processed in a digital logic circuit; and a testing circuit for verifying operations of the converter and the control/interface unit, by controlling the converter.

Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.

Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.

Abstract: The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.

Abstract: A CMOS image sensor according to the present invention has a low-voltage photodiode which is fully depleted at a bias of 1.2-4.5V. The photodiode comprises: a P-epi layer; a field oxide layer dividing the P-epi layer into a field region and an active region; a N− region formed within the P-epi layer, wherein the first impurity region is apart from the isolation layer; and a P0 region of the conductive type formed beneath a surface of the P-epi layer and on the N− region, wherein a width of the P0 region is wider than that of the N− region so that a portion of the P0 region is formed on the P-epi layer, whereby the P0 region has the same potential as the P-epi layer.

Abstract: A CMOS image sensor according to the present invention has a low-voltage photodiode which is fully depleted at a bias of 1.2-4.5V. The photodiode comprises: a P-epi layer; a field oxide layer dividing the P-epi layer into a field region and an active region; a N− region formed within the P-epi layer, wherein the first impurity region is apart from the isolation layer; and a P0 region of the conductive type formed beneath a surface of the P-epi layer and on the N− region, wherein a width of the P0 region is wider than that of the N− region so that a portion of the P0 region is formed on the P-epi layer, whereby the P0 region has the same potential as the P-epi layer.

Abstract: The performance of sigma delta analog to digital conversion systems is enhanced by instrumenting the modulator with an observation circuit which provides quantized estimates of the modulator's state values. These state estimates are filtered separately and the result is added to the output of the decimator. This technique lowers the noise floor of the signal band and achieves performances better than those predicted by the spectrum of the modulator output. Error Correcting is particularly well suited to very low oversampling ratios. Finally, the correction is calculated and added in the digital domain so that this technique can be employed with existing architectures with only minor modifications.

Abstract: A wide dynamic range sensor employing simple sensing circuitry formed on a single chip provides accurate measurements of an incoming signal capable of varying of a wide dynamic range. Responsive to an incoming signal, the sensor generates output pulses having a frequency which is representative of a property of the incoming signal. By measuring the output pulse frequency, an accurate indication of a property of the incoming signal capable of varying over a range of 10.sup.5 or more is possible over the entire signal range. A plurality of sensors can be colocated on a single chip for providing a wide dynamic range sensor array.

Abstract: An array of charge coupled devices (CCD's) is used to perform algorithmic computations on a set of data. The array of CCD's divide, combine and delay the input data to produce output data corresponding to the output desired from the algorithmic computations. Data may be processed in parallel, and the array is preferably divided into pipelined multiple stages so that multiple calculations may be performed in parallel. Processing elements may be interspersed between groups of CCD's to heighten processing capability. The array is particularly useful in a focal plane image processor. In such an image processor, an imager and array are integrated and may be formed on a single chip. Such an image processor can perform Gaussian as well as Laplacian convolutions. It performs all computations in real time. Also useful in the image processor is a device that substracts electric charges and a device that implements conditional summing.