Abstract: There is provided a method of decoding an image, the method comprising: decoding information for motion information prediction of a current block from a bitstream, predicting motion information of the current block based on the information, refining motion information of the current block by using the decoded information and the predicted motion information of the current block and reconstructing the current block based on the refined motion information of the current block.

Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide has a layered crystal structure of space group R3m, includes the nickel (Ni) in an amount of 60 mol % or less based on a total amount of transition metals, includes the cobalt (Co) in an amount greater than an amount of the manganese (Mn), and is composed of single particles.

Abstract: A display device includes a first substrate. A transistor is disposed on the first substrate. A light-emitting element is connected to the transistor. An insulating layer is disposed between the transistor and the light-emitting element. A second substrate at least partially overlaps the first substrate. A color conversion layer is disposed on the second substrate. The insulating layer includes a first insulating layer and a second insulating layer. A distance between the first insulating layer and the first substrate is less than a distance between the second insulating layer and the first substrate. The first insulating layer includes a light blocking material.

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: The present invention relates to a micro-fluid chip for blood vessel formation. The micro-fluid chip of the present invention is constituted by first to fifth channels arranged adjacent to one another on a substrate in sequence, and two or more micro-structures or micro-posts having a gap therebetween are disposed on the interface that each channel forms together with an adjacent channel while contacting the same. Each channel performs a fluidic interaction with a different channel through the gap formed by the micro-structures, and biochemical materials can move therethrough. The micro-fluid chip, according to the present invention, provides a micro-blood vessel having a flat and continuous blood vessel interface outside a body. Furthermore, cancer angiogenesis, cancer intravasation, and cancer extravasation can be modeled using the micro-fluid chip of the present invention. In addition, the micro-fluid chip of the present invention can be used to screen candidate anti-cancer drugs.

Abstract: An apparatus to display a three-dimensional (3D) User Interface (UI) includes a display panel to display a 3D UI comprising main menu polygonal cells; a sensing unit to sense a user selection of a target main menu polygonal cell; and a control unit to execute a function of the selected target main menu polygonal cell.

Abstract: An edge triggered flip-flop including at least one inverter and at least one transmission gate section. Each transmission gate section includes an upper part having a first transmission gate and a second transmission gate connected in series, the first transmission gate being controlled in accordance with a clock signal, and the second transmission gate being controlled in accordance with an enable clock signal. Each transmission gate section also includes a lower part having a third transmission gate and a fourth transmission gate connected in series, the third transmission gate being controlled complementarily to the first transmission gate in accordance with the clock signal, and the fourth transmission gate being controlled complementarily to the second transmission gate in accordance with the enable clock signal.

Abstract: Embodiments relate to a cell library for an application specific integrated circuit (ASIC). Embodiments relate to a method for defining current drive capacity of a cell library, which may define an amount of various kinds of drive current in a single pin and driving current in the cell library. According to embodiments, a method may include defining a current drive capacity for the cell library, receiving a timing arc selected by an external control switch, checking a current drive level defined in the input timing arc, searching for an index table defined in the checked current drive level, and driving a current written on the searched index table.