Abstract: A circuit includes a converter that samples a signal read from a storage medium to generate a sample. The signal includes a physical address of data read from a track on the storage medium. A timing control device generates a clock signal based on a deviation of the track from a reference line. A scaling device generates a scale factor based on the clock signal. A multiplier multiplies the sample by the scale factor to generate a scaled sample. An integrator integrates the scaled sample over a period of the clock signal to generate a resultant value. A comparator compares the resultant value to a threshold to generate an output. The output indicates whether no phase imperfection exists in the scaled sample. A decoder, based on the output of the comparator, decodes the resultant value to obtain the physical address of the data.

Abstract: A circuit including a wobble signal phase imperfection detector configured to detect and correct a phase transition imperfection in a first scaled wobble signal sample. The wobble signal phase imperfection detector includes an integrator configured to integrate the first scaled wobble signal sample over substantially a half-period portion of the wobble clock signal, and a selector configured to select as an output either i) the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal or ii) the first scaled wobble signal sample integrated over substantially the half-period portion of the wobble clock signal, wherein selection of the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal indicates that the phase transition imperfection does not exist with the first scaled wobble signal sample.

Abstract: In a circuit, a wobble detector detects a wobble signal from an optical recording medium and a synchronization signal based on the wobble signal and provides a wobble clock signal. A wobble signal phase imperfection detector responds to the wobble signal and detects and corrects a phase transition imperfection in the wobble signal. The imperfection detector integrates a first scaled wobble signal sample over a half period portion of the wobble clock signal; compares the first scaled wobble signal sample integrated over one period of the wobble clock signal to a variable threshold value; and based on the comparison, outputs either the half period integrated and scaled wobble sample or the first scaled wobble sample integrated over one period of the wobble clock signal. The imperfection detector further decodes the output to obtain wobble address period data.

Abstract: A sync finder includes a pulse jitter detect module to select N-bit segments of an M-bit sync pattern at predetermined positions and to compare the N-bit segments to expected N-bit segments. A pulse verifying module generates a first signal in response to the expected N-bit segments matching the N-bit segments. N and M are integers greater than 1 and M>N.

Abstract: A sync finder module for an optical medium playback device that generates a bit stream including sync patterns and data blocks comprises a pulse jitter detect module that receives the sync pattern, which includes a plurality of transitions each having a desired position in the sync pattern, that selects actual N-bit segments of the sync pattern at the desired positions and that compares the actual N-bit segments to at least one expected N-bit segment. A pulse verifying module communicates with the pulse jitter detect module and generates a verified signal if the expected N-bit segments match the actual N-bit segments.

Abstract: A sync finder module for an optical medium playback device that generates a bit stream including sync patterns and data blocks comprises a pulse jitter detect module that receives the sync pattern, which includes a plurality of transitions each having a desired position in the sync pattern, that selects actual N-bit segments of the sync pattern at the desired positions and that compares the actual N-bit segments to at least one expected N-bit segment. A pulse verifying module communicates with the pulse jitter detect module and generates a verified signal if the expected N-bit segments match the actual N-bit segments.