Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Abstract: An embodiment memory device includes a drain electrode disposed on a semiconductor substrate, a channel region in contact with the drain electrode, a source electrode in contact with the channel region, and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region including a nano-dot region including at least one nano-dot gate, wherein the drain electrode is overlapped with the nano-dot region, and wherein the nano-dot region is overlapped with the channel region.

Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Abstract: An electric field variable gas sensor includes a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a semiconductor thin film material disposed on a part of the semiconductor substrate and a part of the insulating film, a gas molecule adsorption inducing material disposed on the semiconductor thin film material, a first electrode disposed on the semiconductor substrate to be spaced apart from the semiconductor thin film material, and a second electrode disposed on the insulating film to be connected with the semiconductor thin film material.

Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Abstract: The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.

Abstract: The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.

Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.

Abstract: Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a first voltage to the gate, and adsorbing ions on a surface of the CNT.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a first voltage to the gate, and adsorbing ions on a surface of the CNT.