Abstract: A semiconductor chip includes a base substrate including a first surface, a second surface opposite to the first surface, and a sidewall extending between the first surface and the second surface, and a device layer on the first surface of the base substrate, wherein the base substrate includes a stress relief region within a first depth from the second surface and a second depth from the sidewall, and at least a portion of the sidewall of the base substrate is recessed inward from the sidewall of the device layer.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate and including a first chip pad and a first upper insulating layer on sidewalls of the first chip pad, a first bonding wire on a top surface of the first chip pad and connected to the first chip pad, and a second semiconductor chip on a top surface of the first semiconductor chip and spaced apart from the first chip pad, wherein the second semiconductor chip includes a second semiconductor die and a second lower insulating layer on a bottom surface of the second semiconductor die, wherein the second lower insulating layer may be directly bonded to the first upper insulating layer by a chemical bond between the first upper insulating layer and the second lower insulating layer.

Abstract: A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

Abstract: A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.

Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

Abstract: A service-oriented system architecture includes a computer-implemented search method and computer-implemented agent system for enabling efficient information searches on, for example, on XML databases, relational databases, and files located on intranets, the Internet, or other computer network systems. Referred to as the Knowledge Sifter architecture, the architecture may comprise, in one embodiment, a community of cooperating agents. The system architecture may be employed using a variety of methodologies, such as a case-based framework, collaborative filtering, or hybrid filtering. The case-based framework may be configured to recommend query specifications and refinements based on previously-stored user-query cases. Collaborative filtering involves the architecture recommending a set of unseen items that are preferred by other users to the active user. Hybrid filtering combines collaborative filtering and content-based filtering.

Abstract: Disclosed is a computer-implemented search method and computer-implemented agent system for efficient searching of information. Information may be located, for example, on XML databases, relational databases and files located on intranets and the Internet or other like computer network systems. Specifically, a service-oriented system architecture (also referred to as the Knowledge Sifter architecture), may be comprised of a community of cooperating agents. The system architecture may further be employed using a case-based framework configured to recommend query specifications and refinements based on previously-stored user-query cases. Other methodologies such as collaborative filtering, wherein the architecture can recommend a set of unseen items that are preferred by other users to the active user, can be used. Additionally, a hybrid filtering approach which combines both collaborative filtering and content-based filtering can be used effectively in the Knowledge Sifter architecture.

Abstract: Disclosed is a search mechanism comprising: accepting search intent information from a user having a search intent; creating a semantic taxonomy tree having term(s) representative of the search intent information; augmenting the term(s) with associated concepts derived from the term(s) using existing terminological data; associating a weight with at least one of the term(s); obtaining user preference intent; determining root term(s); transforming the semantic taxonomy tree to a Boolean search query; submitting the Boolean search query to searcher(s); receiving at least one search result(s); interpreting the search result(s); requesting page(s) specified the search result(s); receiving the page(s); generating ranked results; presenting the ranked results to the user; presenting the semantic taxonomy tree to the user; accepting user feedback from the user; and using the user feedback to update the user preference intent.