Abstract: The present disclosure provides a method of preparing a catalyst for synthesizing dimethyl ether or methylacetate from synthetic gas that includes preparing a nanosheet ferrierite zeolite (FER), and co-precipitating the nanosheet ferrierite zeolite and a precursor of a Cu—Zn—Al-based oxide (CZA) to obtain a hybrid CZA/FER catalyst.

Abstract: A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.

Abstract: A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

Abstract: There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked, a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.

Abstract: A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

Abstract: A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.

Abstract: There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked, a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.

Abstract: Disclosed are a tandem catalyst for synthesizing methyl acetate from carbon dioxide, a method for preparing the same, and a method for preparing methyl acetate using the same. The tandem catalyst of the present invention includes a first catalyst having a core-shell structure including a composite metal oxide core and a silica shell surrounding a surface of the composite metal oxide core, and a second catalyst including nano-ferrierite (N-FER) zeolite.

Abstract: A semiconductor device includes a first gate structure including first interlayer dielectric layers and first gate lines that are alternately stacked. The semiconductor device also includes a plurality of first supports passing through the first gate structure. The semiconductor device further includes a second gate structure including second interlayer dielectric layers and second gate lines that are alternately stacked. The semiconductor device additionally includes a plurality of second supports passing through the second gate structure. The semiconductor device moreover includes an isolation structure disposed between the first gate structure and the second gate structure, the isolation structure including one or more first protrusions protruding between the first supports and one or more second protrusions protruding between the second supports.

Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a chuck supporting a substrate; a liquid supply unit configured to supply a liquid to a substrate supported on the chuck; a treating container surrounding the substrate supported on the chuck; and an eccentricity correction unit configured to correct an eccentricity of the substrate supported on the chuck, and wherein the eccentricity correction unit contacts a plurality of points on a side end of the substrate supported on the chuck to match a center of the substrate with a center of the chuck.

Abstract: A secondary battery includes a body including a solid electrolyte layer, and a positive electrode and a negative electrode disposed with the solid electrolyte layer interposed therebetween; and first and second external electrodes respectively disposed on one surface and the other surface of the body, opposite to the one surface, and respectively connected to the positive electrode and the negative electrode, wherein the positive electrode comprises a positive electrode active material layer and a first electrolytic mixing portion disposed at an interface of the positive electrode in contact with the solid electrolyte layer. The first electrolytic mixing portion is a mixture of a positive electrode active material and a liquid phase and/or gel phase electrolyte.

Abstract: Disclosed are a tandem catalyst for synthesizing methyl acetate from carbon dioxide, a method for preparing the same, and a method for preparing methyl acetate using the same. The tandem catalyst of the present invention includes a first catalyst having a core-shell structure including a composite metal oxide core and a silica shell surrounding a surface of the composite metal oxide core, and a second catalyst including nano-ferrierite (N-FER) zeolite.

Abstract: A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.

Abstract: A catalyst for preparing a synthesis gas includes: a mesoporous Al2O3 support including mesopores having a pore size of about 1 nm to about 30 nm; metal nanoparticles supported in the mesopores of the mesoporous Al2O3 support wherein the metal nanoparticles have a particle size of less than or equal to about 20 nm; and a metal oxide coating layer including particles wherein the metal oxide coating layer is coated on the surface of the mesoporous Al2O3 support and includes mesopores having a pore size of about 2 nm to about 50 nm.

Abstract: Disclosed is a method for preparing a synthesis gas. The method may include performing a combined reforming reaction by injecting a reaction gas including water (H2O) and heat-treating it in the presence of the catalyst. The catalyst may include a mesoporous support including regularly distributed mesopores, metal nanoparticles supported on the support, and a metal oxide coating layer coated on a surface of the support.

Abstract: The present disclosure provides a method of preparing a catalyst for synthesizing dimethyl ether or methylacetate from synthetic gas that includes preparing a nanosheet ferrierite zeolite (FER), and co-precipitating the nanosheet ferrierite zeolite and a precursor of a Cu—Zn—Al-based oxide (CZA) to obtain a hybrid CZA/FER catalyst.

Abstract: The present disclosure relates to a ternary catalyst coated with a metal oxide, the ternary catalyst including: a ternary catalyst core including a hydrotalcite support and metal particles dispersed on the support; and a metal oxide shell formed on the ternary catalyst core.

Abstract: The present invention provides a heating tray for a vacuum hopper precharger, wherein a heating part is configured in a tray having a secondary battery mounted thereon to allow heat generated from the heating part to be circulated inside a vacuum hopper precharger and to be transferred to the entire secondary battery so that the activity of an electrolyte inside the secondary battery is improved, and according thereto, a large amount of residual gas and impurities can be discharged so as to increase purity of the secondary battery. Particularly, the secondary battery can be fully charged with an electrolyte inside the vacuum hopper precharger, thereby improving productivity compared to a conventional configuration in which a secondary battery is charged with an electrolyte at 60% to 70% inside a vacuum hopper precharger and then charged with a remaining charge amount in another process so as to be fully charged.

Abstract: The present disclosure provides a method of preparing a catalyst for synthesizing dimethyl ether or methylacetate from synthetic gas that includes preparing a nanosheet ferrierite zeolite (FER), and co-precipitating the nanosheet ferrierite zeolite and a precursor of a Cu—Zn—Al-based oxide (CZA) to obtain a hybrid CZA/FER catalyst.

Abstract: Disclosed are a catalyst used for converting carbon dioxide to methanol by hydrogenation and a method preparing the sane. The caratlys may include: a mesoporous indium oxide; and a catalyst supported on the mesoporous indium oxide. Preferably, a porous structure of the mesoporous indium oxide may have Ia3d symmetry and may include mesopores and micropores interconnecting the mesopores.