Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address.

Abstract: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage.

Abstract: A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address.

Abstract: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage.

Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.

Abstract: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

Abstract: A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.

Abstract: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

Abstract: Provided is a voltage regulator. The voltage regulator includes a level down shifter reducing an applied high voltage, a voltage divider dividing the reduced high voltage to generate a first division result, a comparator comparing a reference voltage to the first division result, and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider. The voltage divider divides the output voltage to generate a second division result serving as a voltage control signal fed back to the level down shifter.

Abstract: The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells. Related devices are also discussed.

Abstract: A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

Abstract: The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

Abstract: A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

Abstract: A charge pump circuit alleviates the body effect of a charge transfer transistor, thereby improving the charge transfer efficiency of the charge transfer transistor and thus pumping efficiency. The charge pump circuit includes a plurality of boosting stages that have input nodes and boosting nodes that are connected in series. Each of the boosting stages includes a charge transfer transistor and a first switch transistor, their respective gates being connected together. A first terminal of the charge transfer transistor is connected to one of the input nodes, and a second terminal of the charge transfer transistor is connected to one of the boosting nodes. The first switch transistor makes the voltage level at the bulk of the charge transfer transistors equal to the voltage level at the first terminal of the charge transfer transistor while charges are being transferred through the charge transfer transistor.