Abstract: A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main memory. The N-way cache memory system includes N cache memory blocks receiving a tag field and an offset field of an address bus, a logic OR element for performing a logic OR operation with way hit signals from each cache memory block and for generating a cache hit signal when a way hit signal is produced in one of the cache memory blocks, and a first selection element for outputting data to a data bus, which results from the cache memory blocks in response to the way hit signal.