Patents by Inventor Woo-kang Jin

Woo-kang Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10826399
    Abstract: A method includes generating a gain transition signal in response to any one of an average value of a feedback signal, a slope of the feedback signal, a slope of an input signal of the power converter, a maximum value of the input signal, and a minimum value of the input signal, and generating a first gain control signal and a second gain control signal in response to the gain transition signal. A gain transition controller includes a transition signal generator generating the gain transition signal and a gain control signal generator generating the first gain control signal and the second gain control signal in response to the gain transition signal.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hyun-Chul Eum, Tae-Sung Kim, Young-Mo Yang, Sung-Won Yun, Woo-Kang Jin
  • Publication number: 20190252984
    Abstract: A method includes generating a gain transition signal in response to any one of an average value of a feedback signal, a slope of the feedback signal, a slope of an input signal of the power converter, a maximum value of the input signal, and a minimum value of the input signal, and generating a first gain control signal and a second gain control signal in response to the gain transition signal. A gain transition controller includes a transition signal generator generating the gain transition signal and a gain control signal generator generating the first gain control signal and the second gain control signal in response to the gain transition signal.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hyun-Chul EUM, Tae-Sung KIM, Young-Mo YANG, Sung-Won YUN, Woo-Kang JIN
  • Patent number: 10291130
    Abstract: A method includes generating a first gain control signal and a second gain control signal in response to a gain transition signal indicating a transition of a power converter from a first gain mode to a second gain mode. The method further includes causing the power converter to enter the first gain mode in response to the first gain control signal, and causing the power converter to enter the second gain mode in response to the second gain control signal. A circuit includes a gain transition controller generating a first gain control signal and a second gain control signal in response to a gain transition signal, and a gain control circuit causing the power converter to enter the first gain mode in response to the first gain control signal and causing the power converter to enter the second gain mode in response to the second gain control signal.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 14, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hyun-Chul Eum, Tae-Sung Kim, Young-Mo Yang, Sung-Won Yun, Woo-Kang Jin
  • Publication number: 20170353167
    Abstract: A method includes generating a first gain control signal and a second gain control signal in response to a gain transition signal indicating a transition of a power converter from a first gain mode to a second gain mode. The method further includes causing the power converter to enter the first gain mode in response to the first gain control signal, and causing the power converter to enter the second gain mode in response to the second gain control signal. A circuit includes a gain transition controller generating a first gain control signal and a second gain control signal in response to a gain transition signal, and a gain control circuit causing the power converter to enter the first gain mode in response to the first gain control signal and causing the power converter to enter the second gain mode in response to the second gain control signal.
    Type: Application
    Filed: May 24, 2017
    Publication date: December 7, 2017
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
    Inventors: Hyun-Chul EUM, Tae-Sung KIM, Young-Mo YANG, Sung-Won YUN, Woo-Kang JIN
  • Publication number: 20130300391
    Abstract: An exemplary embodiment of the present invention generates a plurality of clock signals having a frequency according to an output voltage, a plurality of low clock signals of which frequencies are half of frequencies of the plurality of clock signals, and a phase signal corresponding to the output voltage by subtracting an average phase error from a count signal sampled by being synchronized with a reference clock signal from the count result of a first clock signal having the earliest phase among the plurality of clock signals. The average phase error is generated according to a comparison result of a first low clock signal corresponding to the first clock signal and each of other low clock signals among the plurality of low clock signals by being synchronized with the reference clock signal.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 14, 2013
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.
    Inventors: Sung-Pah LEE, Kun-Hee CHO, Woo-Kang JIN
  • Patent number: 7844651
    Abstract: An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Kang Jin, Yun-Cheol Han
  • Patent number: 7599270
    Abstract: A wobble signal for an optical storage device is generated by adjusting a center frequency (?0) of a band pass filter based on an expected frequency of the wobble signal and/or an estimated position of a pick-up apparatus and filtering an input signal corresponding to the wobble signal from the pick-up apparatus with the adjusted band pass filter to provide the wobble signal. Adjusting the center frequency (?0) of the band pass filter may also be based on a measured phase change of the band pass filter. Systems for generating a wobble signal, wobble signal detection circuits and optical storage devices are also provided.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woo-Kang Jin
  • Publication number: 20060044961
    Abstract: A wobble signal for an optical storage device is generated by adjusting a center frequency (?0) of a band pass filter based on an expected frequency of the wobble signal and/or an estimated position of a pick-up apparatus and filtering an input signal corresponding to the wobble signal from the pick-up apparatus with the adjusted band pass filter to provide the wobble signal. Adjusting the center frequency (?0) of the band pass filter may also be based on a measured phase change of the band pass filter. Systems for generating a wobble signal, wobble signal detection circuits and optical storage devices are also provided.
    Type: Application
    Filed: October 19, 2004
    Publication date: March 2, 2006
    Inventor: Woo-Kang Jin
  • Publication number: 20050174189
    Abstract: An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 11, 2005
    Inventors: Woo-Kang Jin, Yun-Cheol Han
  • Patent number: 6771122
    Abstract: A DC offset compensation circuit, and method thereof are capable of reducing the settling time of an output signal through fast compensation of a DC offset of the output signal although a DC voltage of an input signal varies in a closed loop operational amplifier. The DC offset compensation circuit of a closed loop operational amplifier includes a first closed loop operational amplifier and a second closed loop operational amplifier. The first closed loop operational amplifier amplifies an input signal based on a compensation voltage. The second closed loop operational amplifier amplifies a signal output from the first closed loop operational amplifier based on a reference voltage to generate a final output signal.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 3, 2004
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Woo-kang Jin, Moon-sik Song
  • Publication number: 20030206054
    Abstract: A DC offset compensation circuit, and method thereof are capable of reducing the settling time of an output signal through fast compensation of a DC offset of the output signal although a DC voltage of an input signal varies in a closed loop operational amplifier. The DC offset compensation circuit of a closed loop operational amplifier includes a first closed loop operational amplifier and a second closed loop operational amplifier. The first closed loop operational amplifier amplifies an input signal based on a compensation voltage. The second closed loop operational amplifier amplifies a signal output from the first closed loop operational amplifier based on a reference voltage to generate a final output signal.
    Type: Application
    Filed: March 21, 2003
    Publication date: November 6, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Woo-kang Jin, Moon-sik Song