Abstract: A display device can include a light-emitting element, a driving transistor providing a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors controlling driving of the driving transistor are disposed on a display panel. A gate driving circuit supplies scan signals to the display panel through gate lines. An emission driving circuit supplies a plurality of emission signals to the display panel through a plurality of emission signal lines. A data driving circuit supplies a data voltage to the display panel. A timing controller divides the display panel into a plurality of blocks and controls a level of a bias voltage applied to the driving transistor of a corresponding block among the plurality of blocks according to a grayscale of the data voltage supplied to the corresponding block in a low-speed mode operating at a low-speed driving frequency.

Abstract: An electroluminescent display device using a variable refresh rate (VRR) mode. The occurrence of a difference in luminance at a time point of a refresh rate change is reduced, thereby preventing viewers from perceiving the change of the refresh rate.

Abstract: Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

Abstract: Disclosed is a display device comprising a light emitting element, and a pixel driving circuit connected to the light emitting element and configured to include first to fourth nodes, wherein the pixel driving circuit includes a driving transistor connected to the first to third nodes, a plurality of switching transistors, a storage capacitor, and a plurality of signals and voltage lines, wherein an initialization voltage applied through an initialization line among the plurality of signals and voltage lines is varied based on a data voltage.

Abstract: An electroluminescent display device using a variable refresh rate (VRR) mode. The occurrence of a difference in luminance at a time point of a refresh rate change is reduced, thereby preventing viewers from perceiving the change of the refresh rate.

Abstract: The present disclosure relates to a display driver and a display device using the same. The display device according to the embodiment improves an effect of preventing leakage current of a data supply transistor by adaptively controlling and supplying, on the basis of a luminance value of an input data, a parking voltage which is applied in order to prevent the leakage current of the data supply transistor. The display driver comprises a controller which provides a clock signal swinging between a high level and a low level during a refresh frame in which a data voltage is written in a pixel, and provides a clock signal having a direct current voltage during a hold frame in which the data voltage written in the pixel is maintained; a data driver which supplies the data voltage to the pixel during the refresh frame in accordance with a data control signal of the controller; and a power supplier which supplies a parking voltage to the pixel during the hold frame.

Abstract: Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

Abstract: An electroluminescent display device using a variable refresh rate (VRR) mode. The occurrence of a difference in luminance at a time point of a refresh rate change is reduced, thereby preventing viewers from perceiving the change of the refresh rate.

Abstract: Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

Abstract: An electroluminescent display device using a variable refresh rate (VRR) mode. The occurrence of a difference in luminance at a time point of a refresh rate change is reduced, thereby preventing viewers from perceiving the change of the refresh rate.

Abstract: The present disclosure relates to a display driver and a display device using the same. The display device according to the embodiment improves an effect of preventing leakage current of a data supply transistor by adaptively controlling and supplying, on the basis of a luminance value of an input data, a parking voltage which is applied in order to prevent the leakage current of the data supply transistor. The display driver comprises a controller which provides a clock signal swinging between a high level and a low level during a refresh frame in which a data voltage is written in a pixel, and provides a clock signal having a direct current voltage during a hold frame in which the data voltage written in the pixel is maintained; a data driver which supplies the data voltage to the pixel during the refresh frame in accordance with a data control signal of the controller; and a power supplier which supplies a parking voltage to the pixel during the hold frame.

Abstract: Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

Abstract: A liquid crystal display device includes a plurality of data lines; a plurality of gate lines and a pixel array including a plurality of subpixels formed of first-color to fourth-color subpixels. The plurality of subpixels has a first arrangement or a second arrangement. The first arrangement is an arrangement in which in each row of the pixel array two of the first-color to fourth-color subpixels is interleaved. The second arrangement is a different arrangement than the first arrangement in which in each row of the pixel array two of the first-color to fourth-color subpixels are interleaved. A data driver is configured to drive the pixel array according to a first driving method when the pixel array has the first arrangement and drive the pixel array according to at least one second driving method that is different from the first driving method when the pixel array has the second arrangement.

Abstract: A display device is disclosed. A display panel includes a plurality of subpixels of a plurality of colors arranged in a matrix form, and a plurality of gate lines and data lines respectively connected to the subpixels. A data driver is configured to supply data voltages to the subpixels through a plurality of source channels and the data lines. A switch circuit is configured to connect one of the source channels selectively to one of the data lines during a first scan period in one horizontal period and to a different one of the data lines during a second scan period in the one horizontal period. The data driver is configured to supply data voltages of one color to the one of the source channels during both the first scan period and the second scan period in the one horizontal period.

Abstract: A display device includes a pixel array including a first set of subpixels of first to fourth colors and a second set of subpixels of the first to fourth colors. The display device also includes a data driver configured to generate first data voltages and second data voltages. The first data voltages have a first polarity with respect to a common voltage that is applied to the pixel array and the second data voltages have a second polarity with respect to the common voltage that is different than the first polarity. The data driver applies the first data voltages of the first polarity to the first set of subpixels of the first to fourth colors via the data line and subsequently applies the second data voltages of the second polarity to the second set of subpixels of the first to fourth colors via the data line.

Abstract: A liquid crystal display is disclosed. The liquid crystal display includes subpixels of first to fourth colors arranged on each row, a first data line connected to the first color subpixel and the second color subpixel on each row, a second data line connected to the third color subpixel and the fourth color subpixel on each row, a first gate line connected on each row to subpixels of two colors selected among the first to fourth colors, a second gate line connected on each row to subpixels of two remaining colors among the first to fourth colors, a data driver configured to supply a data voltage to the first and second data lines in a time-division manner, and a gate driver configured to supply a gate pulse to the first and second gate lines in synchronization with an output timing of the data voltage.

Abstract: A display device includes a pixel array having a plurality of pixels arranged in a matrix form based on a crossing structure of data lines and gate lines, a data driver having a plurality of output channels and configured to output a data voltage, a multiplexer configured to distribute the data voltage output from the data driver to the data lines in response to first and second control signals, and a gate driver configured to output a gate pulse synchronized with the data voltage in a non-sequential manner. The first and second control signals are in antiphase, and a switching cycle of the first and second control signals is one horizontal period or two horizontal periods.

Abstract: A liquid crystal display device includes a plurality of data lines; a plurality of gate lines and a pixel array including a plurality of subpixels formed of first-color to fourth-color subpixels. The plurality of subpixels has a first arrangement or a second arrangement. The first arrangement is an arrangement in which in each row of the pixel array two of the first-color to fourth-color subpixels is interleaved. The second arrangement is a different arrangement than the first arrangement in which in each row of the pixel array two of the first-color to fourth-color subpixels are interleaved. A data driver is configured to drive the pixel array according to a first driving method when the pixel array has the first arrangement and drive the pixel array according to at least one second driving method that is different from the first driving method when the pixel array has the second arrangement.

Abstract: A display device is disclosed. A display panel includes a plurality of subpixels of a plurality of colors arranged in a matrix form, and a plurality of gate lines and data lines respectively connected to the subpixels. A data driver is configured to supply data voltages to the subpixels through a plurality of source channels and the data lines. A switch circuit is configured to connect one of the source channels selectively to one of the data lines during a first scan period in one horizontal period and to a different one of the data lines during a second scan period in the one horizontal period. The data driver is configured to supply data voltages of one color to the one of the source channels during both the first scan period and the second scan period in the one horizontal period.

Abstract: A liquid crystal display is disclosed. The liquid crystal display includes subpixels of first to fourth colors arranged on each row, a first data line connected to the first color subpixel and the second color subpixel on each row, a second data line connected to the third color subpixel and the fourth color subpixel on each row, a first gate line connected on each row to subpixels of two colors selected among the first to fourth colors, a second gate line connected on each row to subpixels of two remaining colors among the first to fourth colors, a data driver configured to supply a data voltage to the first and second data lines in a time-division manner, and a gate driver configured to supply a gate pulse to the first and second gate lines in synchronization with an output timing of the data voltage.