Patents by Inventor Woon KANG

Woon KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package and manufacturing method therefor
    Patent number: 12708031
    Abstract: A semiconductor package comprises: a printed circuit board including a connection portion; an IC chip arranged on the printed circuit board; a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion; a bonding layer arranged between the solder portion and the connection portion; and an underfill arranged between the IC chip and the printed circuit board, wherein the bonding layer includes thermosetting resin, and the underfill include thermoplastic resin.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: August 11, 2026
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sup Choi, Woon Kang, Jin Ho Yoon
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
    Publication number: 20240234364
    Abstract: A semiconductor package comprises: a printed circuit board including a connection portion; an IC chip arranged on the printed circuit board; a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion; a. bonding layer arranged between the solder portion and the connection portion; and an underfill arranged between the IC chip and the printed circuit board, wherein the bonding layer includes thermosetting resin, and the underfill include thermoplastic resin.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 11, 2024
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Tae Sup CHOI, Woon KANG, Jin Ho YOON
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
    Publication number: 20240136322
    Abstract: A semiconductor package comprises: a printed circuit board including a connection portion; an IC chip arranged on the printed circuit board; a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion; a. bonding layer arranged between the solder portion and the connection portion; and an underfill arranged between the IC chip and the printed circuit board, wherein the bonding layer includes thermosetting resin, and the underfill include thermoplastic resin.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 25, 2024
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Tae Sup CHOI, Woon KANG, Jin Ho YOON