Abstract: A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.

Abstract: A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.

Abstract: A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.

Abstract: Semiconductor devices are provided including an internal circuit on a front side of a substrate, the substrate defining a through-silicon via (TSV) structure extending vertically therein; a back side insulating layer on a back side of the substrate; and a back side bonding structure on the back side insulating layer. The TSV structure includes a front side end on a front side of the substrate and contacts the internal circuit and a back side end extending toward a back side of the substrate. The back side bonding structure includes a back side bonding interconnection portion on the back side insulating layer defining a back side bonding via hole therein and a back side bonding via plug portion in the contact plug hole in the back side insulating layer connected to a back side end of the TSV structure.

Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.

Abstract: Semiconductor devices are provided including an internal circuit on a front side of a substrate, the substrate defining a through-silicon via (TSV) structure extending vertically therein; a back side insulating layer on a back side of the substrate; and a back side bonding structure on the back side insulating layer. The TSV structure includes a front side end on a front side of the substrate and contacts the internal circuit and a back side end extending toward a back side of the substrate. The back side bonding structure includes a back side bonding interconnection portion on the back side insulating layer defining a back side bonding via hole therein and a back side bonding via plug portion in the contact plug hole in the back side insulating layer connected to a back side end of the TSV structure.

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.