Patents by Inventor Woon Yik Yong
Woon Yik Yong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817407Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.Type: GrantFiled: May 17, 2022Date of Patent: November 14, 2023Assignee: Infineon Technologies AGInventors: Shao Ping Wan, Eric Brion Acquitan, Dexter Reynoso, Jürgen Schredl, Woon Yik Yong
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Patent number: 11444011Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.Type: GrantFiled: November 12, 2020Date of Patent: September 13, 2022Assignee: Infineon Technologies AGInventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
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Publication number: 20220278060Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Inventors: Shao Ping Wan, Eric Brion Acquitan, Dexter Reynoso, Jürgen Schredl, Woon Yik Yong
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Publication number: 20220181280Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A breakdown voltage of the electrically insulative material is greater than a breakdown voltage of the mold compound.Type: ApplicationFiled: December 7, 2020Publication date: June 9, 2022Inventors: Shao Ping Wan, Eric Brion Acquitan, Dexter Reynoso, Jürgen Schredl, Woon Yik Yong
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Patent number: 11355460Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A breakdown voltage of the electrically insulative material is greater than a breakdown voltage of the mold compound.Type: GrantFiled: December 7, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Shao Ping Wan, Eric Brion Acquitan, Dexter Reynoso, Jürgen Schredl, Woon Yik Yong
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Publication number: 20210066172Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.Type: ApplicationFiled: November 12, 2020Publication date: March 4, 2021Inventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
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Patent number: 10872848Abstract: An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe.Type: GrantFiled: October 25, 2018Date of Patent: December 22, 2020Assignee: Infineon Technologies AGInventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
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Publication number: 20200135626Abstract: An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
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Patent number: 9082737Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.Type: GrantFiled: November 15, 2012Date of Patent: July 14, 2015Assignee: Infineon Technologies AGInventors: Carlo Baterna Marbella, Ganesh Vetrivel Periasamy, Woon Yik Yong, Kok Kiat Koo, Christian Arndt, Edward Myers
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Publication number: 20140131844Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Carlo Baterna Marbella, Ganesh Vetrivel Periasamy, Woon Yik Yong, Kok Kiat Koo, Christian Arndt, Edward Myers