Patents by Inventor Woong-Hee Sohn
Woong-Hee Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10373831Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.Type: GrantFiled: July 17, 2017Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-won Yu, Hyun-suk Lee, Ji-woon Park, Gi-hee Cho, Hee-sook Park, Woong-hee Sohn
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Patent number: 10103152Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: GrantFiled: June 27, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hoon Kim, Eun Tae Kim, Seong Hun Park, Youn Jae Cho, Hee Sook Park, Woong Hee Sohn, Jin Ho Oh
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Publication number: 20180053769Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: ApplicationFiled: June 27, 2017Publication date: February 22, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hoon KIM, Eun Tae KIM, Seong Hun PARK, Youn Jae CHO, Hee Sook PARK, Woong Hee SOHN, Jin Ho OH
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Publication number: 20180019125Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.Type: ApplicationFiled: July 17, 2017Publication date: January 18, 2018Inventors: Ji-won YU, Hyun-suk LEE, Ji-woon PARK, Gi-hee CHO, Hee-sook PARK, Woong-hee SOHN
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Publication number: 20170309491Abstract: A method of forming a tungsten film including disposing a substrate inside a process chamber; performing a tungsten nucleation layer forming operation for forming a tungsten nucleation layer on the substrate, performing a first operation for forming a portion of a tungsten bulk layer on the tungsten nucleation layer by alternately supplying a tungsten-containing gas and a reducing gas into the process chamber, and performing a second operation for stopping the supply of the tungsten-containing gas and the reducing gas and removing a remaining gas in the process chamber may be provided. The first operation and the second operation may be repeated at least twice until the tungsten bulk layer reaches a desired thickness.Type: ApplicationFiled: December 5, 2016Publication date: October 26, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-ku AHN, Ji-hoon KIM, Seong-hun PARK, Youn-jae CHO, Hee-sook PARK, Woong-hee SOHN
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Patent number: 9184178Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.Type: GrantFiled: December 9, 2014Date of Patent: November 10, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
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Patent number: 9178039Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.Type: GrantFiled: October 11, 2013Date of Patent: November 3, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hwa Park, Woong-Hee Sohn, Man-Sug Kang, Hee-Sook Park
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Publication number: 20150091078Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.Type: ApplicationFiled: December 9, 2014Publication date: April 2, 2015Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
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Publication number: 20150017797Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Jae-hwa PARK, Man-sug KANG, Hee-sook PARK, Woong-hee SOHN
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Patent number: 8916922Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.Type: GrantFiled: December 21, 2012Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
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Publication number: 20140159145Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.Type: ApplicationFiled: October 11, 2013Publication date: June 12, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hwa PARK, Woong-Hee SOHN, Man-Sug KANG, Hee-Sook PARK
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Publication number: 20140070300Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.Type: ApplicationFiled: December 21, 2012Publication date: March 13, 2014Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
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Patent number: 8486783Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.Type: GrantFiled: February 11, 2010Date of Patent: July 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-hee Sohn, Byung-hee Kim, Dae-yong Kim, Min-sang Song, Gil-heyun Choi, Kwang-jin Moon, Hyun-su Kim, Jang-hee Lee, Eun-ji Jung, Eun-ok Lee
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SEMICONDUCTOR DEVICE INCLUDING METAL-CONTAINING CONDUCTIVE LINE AND METHOD OF MANUFACTURING THE SAME
Publication number: 20130075909Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Inventors: Jae-hwa PARK, Man-sug KANG, Hee-sook PARK, Woong-hee SOHN -
Patent number: 8173506Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.Type: GrantFiled: November 30, 2009Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ji Jung, Hyun-soo Kim, Byung-hee Kim, Dae-yong Kim, Woong-hee Sohn, Kwang-jin Moon, Jang-hee Lee, Min-sang Song, Eun-ok Lee
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Patent number: 8119526Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.Type: GrantFiled: November 29, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ji Jung, Woong-hee Sohn, Su-kyoung Kim, Gil-heyun Choi, Byung-hee Kim
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Patent number: 8034701Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.Type: GrantFiled: July 31, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
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Publication number: 20110201198Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.Type: ApplicationFiled: November 29, 2010Publication date: August 18, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-ji JUNG, Woong-hee SOHN, Su-kyoung KIM, Gil-heyun CHOI, Byung-hee KIM
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Patent number: 7897500Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.Type: GrantFiled: November 24, 2008Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ji Jung, Dae-yong Kim, Gil-heyun Choi, Byung-hee Kim, Woong-hee Sohn, Hyun-su Kim, Jang-hee Lee, Eun-ok Lee, Jeong-gil Lee
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Patent number: 7879737Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: GrantFiled: May 24, 2010Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong