Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Abstract: A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier.

Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.

Abstract: A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Abstract: A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier.

Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.

Abstract: A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Abstract: A semiconductor apparatus includes a first capacitor formed in a normal cell area and including a lower electrode coupled to one end of a cell transistor, and a second capacitor formed in a dummy cell area and including a lower electrode coupled to a power terminal.