Patents by Inventor Woong Kyu CHOI

Woong Kyu CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468080
    Abstract: A memory device includes a first strobe delay circuit delaying a first data strobe signal to generate a delayed first data strobe signal, a first write leveling circuit sampling a first delay clock in synchronization with the delayed first data strobe signal, a second strobe delay circuit delaying a second data strobe signal to generate a delayed second data strobe signal, a replica second strobe delay circuit delaying the first data strobe signal by a delay value obtained by replicating the second strobe delay circuit to generate a replica delayed second data strobe signal; and a second write leveling circuit sampling a second delay clock in synchronization with the delayed second data strobe signal in a first I/O mode, and sampling the second delay clock in synchronization with the replica delayed second data strobe signal in a second I/O mode.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Dae-Ho Yun, Woong-Kyu Choi
  • Patent number: 9793009
    Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 17, 2017
    Assignee: SK hynix Inc.
    Inventors: Woong Kyu Choi, Jong Man Im, Jun Cheol Park
  • Publication number: 20160241141
    Abstract: A voltage generator may include: an internal voltage generation unit suitable for generating an internal voltage by pumping an external voltage in response to a pumping cycle signal; and a capacitance adjusting unit comprising a capacitive element which receives and transmits the pumping cycle signal to the internal voltage generation unit, and is suitable for adjusting a capacitance of the capacitive element based on the external voltage.
    Type: Application
    Filed: June 18, 2015
    Publication date: August 18, 2016
    Inventors: Jong-Man IM, Woong-Kyu CHOI
  • Patent number: 9390997
    Abstract: The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 12, 2016
    Assignee: SK hynix, Inc.
    Inventors: Jong Hoon Kim, Jae Hyun Son, Byoung Do Lee, Kuk Jin Chun, Woong Kyu Choi
  • Publication number: 20160196881
    Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 7, 2016
    Inventors: Woong Kyu CHOI, Jong Man IM, Jun Cheol PARK
  • Patent number: 9324459
    Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: April 26, 2016
    Assignee: SK hynix Inc.
    Inventors: Woong Kyu Choi, Jong Man Im, Jun Cheol Park
  • Publication number: 20150008588
    Abstract: The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.
    Type: Application
    Filed: December 23, 2013
    Publication date: January 8, 2015
    Applicant: SK hynix, Inc.
    Inventors: Jong Hoon KIM, Jae Hyun SON, Byoung Do LEE, Kuk Jin CHUN, Woong Kyu CHOI