Abstract: An address transition detector (ATD) of a semiconductor memory device. In particular, even if the address transition of the semiconductor memory device occurs over a long time, malfunction is prevented by synchronizing outputs of a buffer and a decoder and an output of the ATD circuit. To accomplish this, input block for sensing a high trip level and a low trip level is included in the ATD circuit. Thus, if the address transition occurs slowly over a long time, the duration of a short pulse indicating the address transition becomes long, thereby producing accurate data. Moreover, since the ATD is not restricted to a particular system application, it can be used in a wide variety of applications by adapting a memory device to utilize the ATD.

Abstract: There is provided a high voltage generating circuit including a circuit for sensing a voltage level of a high voltage for erasing and programming operations, a circuit for generating a given reference voltage, a circuit for comparing the sensed high voltage with the reference voltage, a circuit for applying or blocking a pump signal to a high voltage pump circuit according to the compared signal, a circuit for raising the voltage up to a given level under the control of the pump signal, and an EEPROM fuse circuit connected to the circuit for sensing the voltage level of the high voltage or the circuit for generating the given reference voltage and having stored data, whereby the voltage level of the high voltage finally output may be properly maintained and controlled according to the state of the stored data.

Abstract: A program optimizing circuit for an EEPROM array comprising a program voltage generating circuit connected to each of bit lines, an anti-program voltage generating circuit connected between input/output data line and data input/output buffer and circuit for causing column decoder to selectively produce anti-program voltage or column address, is disclosed. The program voltage generating circuit further includes a first high voltage pumping circuit, transfer means and latch circuit. The operation of the first high voltage pumping circuit is controlled by the data stored in the latch circuit. In programming, the anti-program voltage is applied to all the bit lines, so as to prevent the unwanted memory cells from being programmed or erased.

Abstract: An electrically page erasable and programmable read only memory device is an EEPROM device which is erasable page by page, and consists of flash-type floating gate transistors as the memory cells. The memory cell array of the device is divided by a plurality of pages, wherein each page comprises a plurality of bit lines, a plurality of common source lines, and a plurality of word lines. A plurality of erase selection circuits are arranged and correspond to the respective pages in order to erase the cells in a selected page, wherein each erase selection circuit comprises a passing transistor, a gate, a voltage stabilizing transistor, and an erasing line.