Abstract: An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S?) disposed in a non-display region, a plurality of signal lines (111, 112) is provided in the wiring regions (S-S?), at least part of the signal lines (111, 112) within each of the wiring regions (S-S?) are respectively formed by connecting conducting wires (121, 123) located in different layers in series; and any two of the signal lines (111, 112) within a same wiring region (S-S?) have a resistance difference within a threshold range. The same signal line (111, 112) is disposed in different layers, so that the signal line (111, 112) is bent in a plane perpendicular to the array substrate, which achieves of the extension of a length of the signal line (111, 112), and thus increases the length and resistance of the signal line (111, 112), the resistance of which needs to be increased.

Abstract: An array substrate and a display device are provided. The array substrate includes a display region and a peripheral circuit region, wherein a first gate line, a first data line and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region is provided with at least one test unit including: a second gate line; a second data line; a second testing pixel electrode; and a second testing thin film transistor. The second testing thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.

Abstract: An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a plurality of conductive layers (11, 12) in different layers, and the plurality of conductive layers (11, 12) are provided with insulation layers (21) therebetween, and are connected in parallel through one or more vias (3). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.

Abstract: Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.

Abstract: An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S?) disposed in a non-display region, a plurality of signal lines (111, 112) is provided in the wiring regions (S-S?), at least part of the signal lines (111, 112) within each of the wiring regions (S-S?) are respectively formed by connecting conducting wires (121, 123) located in different layers in series; and any two of the signal lines (111, 112) within a same wiring region (S-S?) have a resistance difference within a threshold range. The same signal line (111, 112) is disposed in different layers, so that the signal line (111, 112) is bent in a plane perpendicular to the array substrate, which achieves of the extension of a length of the signal line (111, 112), and thus increases the length and resistance of the signal line (111, 112), the resistance of which needs to be increased.

Abstract: An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a plurality of conductive layers (11, 12) in different layers, and the plurality of conductive layers (11, 12) are provided with insulation layers (21) therebetween, and are connected in parallel through one or more vias (3). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.

Abstract: An array substrate and a display device are provided. The array substrate comprises a display region and a peripheral circuit region (B), wherein a first gate line (20), a first data line (10) and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region (B) is provided with at least one test unit (100) including: a second gate line (101); a second data line (102); a second testing pixel electrode (103); and a second testing thin film transistor (104). The second testing thin film transistor (104) comprises a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.

Abstract: Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.