Abstract: Disclosed herein are methods, systems and devices including a first layer with at least one transistor, a second layer on a first side of the first layer, the second layer including a signal layer. A third layer may be on a second side of the first layer, the second side opposite the first side of the first layer, and the third layer may include a power layer. A stack may be coupled to the second layer, the stack including a first device row and a second device row. Each of the first device row and the second device row may include at least one device such as a computational device. The second device row may be mounted on the first device row, and the devices in the first device row may differ from the devices of the second device row.

Abstract: Provided is a semiconductor package including a silicon substrate including a through-silicon via, a first build-up layer on a first surface of the silicon substrate, a second build-up layer on a second surface of the silicon substrate, and at least one integrated stack capacitor included in at least one of the silicon substrate, the first build-up layer, and the second build-up layer.

Abstract: Provided is a semiconductor device including a substrate including a through via, a first redistribution layer on a first surface of the substrate, a second redistribution layer on a second surface, opposite to the first surface, of the substrate, a semiconductor chip on a second surface of the second redistribution layer, and one or more capacitors included in at least one of the substrate, the first redistribution layer, and the second redistribution layer.

Abstract: Provided is a semiconductor package including a glass substrate including a through-glass via, a first redistribution layer on a lower surface of the glass substrate, a second redistribution layer on an upper surface of the glass substrate, and at least one integrated stack capacitor included in at least one of the glass substrate, the first redistribution layer, and the second redistribution layer.

Abstract: A method, system, and device are disclosed herein where a first layer includes at least one transistor, a second layer on a first side of the first layer includes a signal network, a third layer on a second side of the first layer, opposite the first side, includes a backside power delivery network, and a memory module is coupled to the signal network. The backside power delivery network, the at least one transistor, and the signal network may provide a logic circuit for the memory module.

Abstract: A semiconductor package may include a first redistribution line structure; a die on the first redistribution line structure; a first memory device on a first surface of the die; a second redistribution line structure on a second surface of the die opposite from the first surface; a second memory device on the second redistribution line structure; and at least one semiconductor chip on the second redistribution line structure and electrically connected to the first memory device and to the second memory device. The first memory device may be a static RAM (SRAM), and the second memory device may be a dynamic RAM (DRAM).

Abstract: A method, system and devices are disclosed providing a first layer, the first layer including a first device region and a second device region, and a second layer including an interconnection die, the interconnection die including an interface logic. The first device region and the second device region are mounted on a first side of the interconnection die, and the first device region and the second device region are communicatively coupled to the interface logic.

Abstract: Disclosed herein are methods, systems and devices including a first layer, the first layer including a first compute device, a first multi-device package, and a second multi-device package. The first compute device may be between the first multi-device package and the second multi-device package. A second layer may include a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer electrically connecting the first compute device to the first multi-device package and the first redistribution layer electrically connecting the first compute device to the second multi-device package. The first layer may include a third multi-device package and a fourth multi-device package, with the first compute device between the third multi-device package and the fourth multi-device package.

Abstract: A method, system, and devices are disclosed herein involving a first substrate with a first grain layer, a second substrate with a second grain layer, and a third grain layer contacting the first grain layer and the second grain layer. The third grain layer having an average grain size smaller than the first grain layer and second grain layer.

Abstract: A semiconductor package comprises a core layer, an integrated stack capacitor (ISC) on the core layer, one or more build-up layers on the core layer in which the ISC is embedded, and one or more metal layers on the core layer.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Organic substrates having integrated components and systems and methods for designing and optimizing integrated components for substrates are provided. One embodiment is a computer program embodied in a computer-readable medium for optimizing the design of an integrated inductor in a substrate adapted for use in integrated circuits.