Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.

Abstract: A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.

Abstract: Provided is a processor including an accelerator including a plurality of processing elements, and an accelerator controller configured to allocate at least two processing elements from the plurality of processing elements to a vector lane, and based on a loop operation being included in an instruction set to be processed by the accelerator, release the allocation of the vector lane to suspend a vector operation of the vector lane.

Abstract: An in-register computing (IRC) device includes: a register module including a register bank and an addition device, the register bank including register cells, the register cells including IRC cells, wherein the register module is configured to allocate first of the register cells to an input area, second of the register cells to a weight area, and third of the register cells to an output area, wherein the input area is an area in which the register bank stores an input value, the weight area is an area including one of the IRC cells configured to perform an IRC operation between the input value and a weight value, and the output area is an area configured to store an output value obtained by performing an addition operation on an operation result of the IRC operation using an addition device.

Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

Abstract: Disclosed are an apparatus and method with neural processing. The operating method includes constructing a neuron array including a plurality of neuron modules, mapping a target pattern to the neuron array, adapting the neuron modules to the target pattern in response to a reception of the target pattern, and training the neuron modules to cause the neuron array to mimic the target pattern.