Abstract: We disclose multi-electrode, energy-recycling, resonant stimulation circuits and strategies for energy-efficient blocking of action potentials in nerve. Our schemes increase the probability that most of the electrical stimulation is directed through the nerve rather than dissipated in ohmic extracellular solution alongside it via mechanical and electrical means; they use energy-recycling and resonant-amplification strategies that recycle and amplify capacitive nerve energy such that the nerve itself becomes an integral part of the circuit creating its oscillatory blocking waveform; they use traveling-wave strategies with distributed multi-electrode stimulation that alters the timing and intensity of stimulation at various points along the nerve to synchronize blocking stimulation with wave propagation in the nerve in an energy-efficient fashion.

Abstract: We disclose multi-electrode, energy-recycling, resonant stimulation circuits and strategies for energy-efficient blocking of action potentials in nerve. Our schemes increase the probability that most of the electrical stimulation is directed through the nerve rather than dissipated in ohmic extracellular solution alongside it via mechanical and electrical means; they use energy-recycling and resonant-amplification strategies that recycle and amplify capacitive nerve energy such that the nerve itself becomes an integral part of the circuit creating its oscillatory blocking waveform; they use traveling-wave strategies with distributed multi-electrode stimulation that alters the timing and intensity of stimulation at various points along the nerve to synchronize blocking stimulation with wave propagation in the nerve in an energy-efficient fashion.

Abstract: A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.

Abstract: An ultra-low-power circuit for wireless neural recording and stimulation is provided. The circuit includes a neural amplifier with adaptive power biasing for use in multi-electrode arrays and a decoding and/or learning architecture. An impedance-modulation telemetry system provides low-power data telemetry. Also, the circuit includes a wireless link for efficient power transfer, and at least one circuit for wireless stimulation of neurons.

Abstract: A micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays is provided. The micropower neural amplifier includes a low noise gain stage. The low noise gain stage is implemented using an amplifier and pseudoresistor elements.

Abstract: An ultra-low-power circuit for wireless neural recording and stimulation is provided. The circuit includes a neural amplifier with adaptive power biasing for use in multi-electrode arrays and a decoding and/or learning architecture. An impedance-modulation telemetry system provides low-power data telemetry. Also, the circuit includes a wireless link for efficient power transfer, and at least one circuit for wireless stimulation of neurons.

Abstract: A micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays is provided. The micropower neural amplifier includes a low noise gain stage. The low noise gain stage is implemented using an amplifier and pseudoresistor elements.

Abstract: A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.