Abstract: A row decoder circuit for a non-volatile memory device is disclosed, and the circuit is for erasing, programming and reading the data from the cell comprising of a selecting transistor and a sensing transistor. The required high voltage is supplied to word lines and sense lines from a single high voltage generating section, and when erasing data, a low voltage is supplied to the word line. A transistor for connecting a sense line is connected to each row, in such a manner that the damage liable to occur to the gate oxide layer should be reduced, thereby improving the life expectancy of the chip, and reducing the area of the chip.