Abstract: A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active area. The first gate line includes a first gate part crossing the first active area along a first imaginary line, a second gate part crossing the second active area along a second imaginary line, and a third gate part connecting the first gate part and the second gate part and extending along a third imaginary line crossing the first imaginary line and the second imaginary line. The first gate part, the second gate part and the third gate part are arranged so that the first gate line has a shape of 180° rotational symmetry. A point of the rotational symmetry is located on the first gate part.

Abstract: A method of fabricating semiconductor device is provided that includes a method of forming plugs in a semiconductor device. The plugs or contacts can connect an upper conductive layer to a lower conductive layer. The plugs are preferably formed without providing contact holes. The method of fabricating a semiconductor device can include the steps of defining an active area of a device by forming a field insulating layer on a semiconductor substrate of a first conductivity type, forming a gate oxide on an exposed surface of the active layer and forming a plurality of gates and associated cap insulating layers along a first direction perpendicular to an active area. An impurity region of a second conductivity type is formed in the exposed active area of the semiconductor substrate and a plurality of sidewall spacers are formed at sides of the gates. An electrically-conductive layer is formed for contacting the impurity region between the gates on the semiconductor substrate.

Abstract: The interconnect structure for semiconductor devices includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a first back-up layer on the insulating layer, a first conductive layer on the first back-up layer, a second back-up layer on the first conductive layer, a second conductive layer on the second back-up layer, and a third back-up layer on the second conductive layer. The first and second conductive layers are formed of aluminum-based alloys, and the first to third back-up layers are formed of aless conductive material such as transition metal alloys.

Abstract: A method for fabricating a capacitor in a DRAM cell, includes the steps of: forming a plurality of wordlines each having a first cap insulating film on a semiconductor substrate; forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of each of the wordlines; forming first sidewall insulating films at the both sides of said each of the wordlines; forming first plugs for contacting either capacitor nodes or bitlines on each of the source/drain impurity regions; forming an interlayer insulating film on the semiconductor substrate and forming a contact hole to the first plugs for contacting to the bitlines therein; forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plugs, and having a second cap insulating film; forming second sidewall insulating films at both sides of each of the bitlines and selectively removing the interlayer insulating film to expose surfaces of the first plugs; fo

Abstract: A method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer.

Abstract: Method for forming a wiring in a semiconductor device having a cell array region and a peripheral region, which allows to form a micron pattern below a critical resolution of an exposure, including the steps of (1) forming a conduction layer and a sacrificial wiring layer on a substrate in succession, (2) selectively removing the sacrificial wiring layer to form a virtual wiring line having a sloped end portion, (3) forming sidewall insulating films at sides of the virtual wiring line excluding the sloped end portion, (4) removing the virtual wiring line entirely, (5) forming a mask layer on regions of the pad and peri region pads and other wirings are to be formed thereon, and (6) using the mask layer and the sidewalls in removing the conduction layer selectively, to form a micron pattern.

Abstract: Provided is a semiconductor device, including: a semiconductor substrate; a first conductive type well which is formed on the semiconductor substrate; first and second field oxide layers which are formed on the well, defining the active region of the device; a node junction, where second conductive type impurity ions are heavily doped, making contact with the field oxide layer in the well; a gate electrode formed by interposing a gate oxide layer between the second field oxide layer and the node junction on the well; a switching device made from an interlevel insulating layer, for covering the gate electrode, and having a contact hole exposing the node junction on the semiconductor substrate; a storage electrode which makes contact with the node junction through the contact hole; a dielectric layer formed on the storage electrode; and a memory device made of a plate electrode which is formed on the dielectric layer.

Abstract: A method of forming a capacitor for a DRAM includes the steps of: forming an insulating layer with a contact hole on a substrate; forming a first conductive layer on the insulating layer and in the contact hole; forming a temporary layer pattern on a portion of the first conductive layer corresponding to the contact hole; forming a second conductive layer on the first conductive layer and on the temporary layer pattern; selectively implanting oxygen ions into the first and second conductive layers except a portion of the second conductive layer corresponding to a side face of the temporary layer pattern; heat treating so as to convert the oxygen-ion-implanted first and second conductive layer portions into an oxide; removing the oxide and temporary layer pattern; forming a dielectric layer on the surface of the first and second conductive layers; and forming a third conductive layer on the dielectric layer.