Abstract: An oscillator comprising a first and a second transistor having their sources interconnected via a capacitor and in which each gate is connected to the drain of the other transistor and each drain is connected to a load circuit. A load circuit in the form of a resistor produces a non-linear transfer characteristic. By arranging each load circuit in the form of a parallel combination of two transistors of which a first gate is connected to the drain of the first transistor and of which a second gate is connected to the drain of the second transistor, an oscillator presenting a more linear transfer characteristic is obtained. With different frequency adjusting circuits this transfer characteristic can be realized in a first-order approximation or can even be totally independent of the threshold voltage of the transistors used.

Abstract: A variable gain amplifier stage comprises two field-effect transistor connected as a differential pair with a controlled tail-current source as gain control so that a slope control is obtained. The transistors, connected as a differential pair, each have a field-effect transistor operated in the triode region as a load so that the signal resistance of said transistors is a function of the tail current. The gain factor of the amplifier stage thus is determined by the slope of the amplifier transistor as a function of the tail current and by the signal-current resistance of the load transistors as a function of the control current, which, over a comparatively wide range of tail current, yields a substantially linear relationship between the gain factor expressed in decibels and the tail current.

Abstract: A current stabilizer equipped with field-effect transistors of the enhancement type has two parallel current paths which are coupled by means of two different current coupling circuits in order to obtain a stabilizing point. At least one of the two coupling circuits comprises two field-effect transistors which are each included in one of the two current paths. One of said field-effect transistors has a gate-source voltage which is a constant fraction of the gate-source voltage of the other transistor. This is achieved by including in series with said one transistor, a third field-effect transistor with interconnected gate and drain electrodes so that the other one of said two transistors has a gate-source voltage which is twice as high as that of the said one transistor. The other current coupling circuit is of the opposite conductivity type and may be a current mirror, but it may also comprise the complementary version of the one current coupling circuit.

Abstract: An integrated circuit comprising a plurality of adjustable voltage-current converters, of which one converter is employed as a reference converter. The reference converter is included in a control loop. To the input of the reference converter an input voltage is applied in that a first current is passed through a reference resistor connected to said input. A second current, which is in a fixed ratio to said first current, is compared with the output current of the reference converter and this reference converter is then biassed so that its output current corresponds to said second current. In this way the transconductance of the reference converter is determined by the reference resistor and the ratio of the first and the second current, so that this transconductance is highly independent of process, temperature and supply-voltage variations. The other converters are biassed by signals derived from the bias signals for the reference converter and thus have corresponding transconductances.

Abstract: A differential load circuit comprises first, second, third and fourth field-effect transistors of the same conductivity type having interconnected gate electrodes. The source electrodes of the first and second transistors are connected to a first power supply terminal and the drain electrodes of the third and fourth transistors to a second power supply terminal via quiescent current sources. A first input terminal is connected to the interconnected source and drain electrodes of the third and first transistors and a second input terminal is connected to the interconnected source and drain electrodes of the fourth and second transistors. An output terminal is connected to the drain electrode of the fourth transistor. Biasing means are coupled to the gate electrodes of the four transistors, and supply a voltage to the gate electrodes so that the common-mode drain currents of the third and fourth transistors correspond to the currents supplied by the quiescent current sources.