Abstract: A level shifter includes a cross-coupled transistor pair, first through third cascode transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first cascode transistor pair is controlled by a first reference voltage. The second cascode transistor pair is controlled by a pair of differential control voltages. The third cascode transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second cascode transistor pair.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: A four-phase charge pump circuit provided includes multiple boosting stages. Each boosting stage includes two branch charge pumps. Each branch charge pump includes a main pass transistor and a pre-charge transistor. Two ends of the main pass transistor serve as a first node and a second node of the branch charge pump respectively. A first end, a second end and a control end of the pre-charge transistor are coupled to a control end of the main pass transistor, a second node and a first node of the branch charge pump respectively. At least one boosting stage further includes two auxiliary start-up transistors. Two ends of each auxiliary start-up transistor are coupled to the control end of one main pass transistor and the second node of the branch charge pump respectively. A control end of each auxiliary start-up transistor is coupled to the control end of one main pass transistor.

Abstract: A four-phase charge pump circuit provided includes multiple boosting stages. Each boosting stage includes two branch charge pumps. Each branch charge pump includes a main pass transistor and a pre-charge transistor. Two ends of the main pass transistor serve as a first node and a second node of the branch charge pump respectively. A first end, a second end and a control end of the pre-charge transistor are coupled to a control end of the main pass transistor, a second node and a first node of the branch charge pump respectively. At least one boosting stage further includes two auxiliary start-up transistors. Two ends of each auxiliary start-up transistor are coupled to the control end of one main pass transistor and the second node of the branch charge pump respectively. A control end of each auxiliary start-up transistor is coupled to the control end of one main pass transistor.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

Abstract: A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives an input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.

Abstract: A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: A four-phase charge pump circuit including an output stage and multiple boosting stages is provided. The multiple boosting stages are coupled to the output stage in series, and each of the multiple boosting stages is driven by four-phase clock signals. The output stage is driven by two clock signals of the four-phase clock signals and outputs a positive boosted voltage, and thereby the four-phase charge pump circuit is a positive charge pump circuit. Each of the boosting stages includes two branch charge pumps, and each of the two branch charge pumps includes a main pass transistor and a pre-charge transistor. The main pass transistors and the pre-charge transistors of the boosting stages are disposed on an identical deep doped region.

Abstract: The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal. The clock freezing circuit directly receives the clock signal and an enable signal. The clock freezing circuit decides whether to pass or latch a voltage level of the clock signal according to the enable signal to generate a controlled clock signal. The charge pump circuit directly receives the controlled clock signal and operates a charge pump operation on an input voltage to generate a pumping voltage.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.

Abstract: A charge pump circuit has an input stage, an output stage and multiple boosting stages coupled between the input stage and the output stage. The boosting stages are driven by four phase clock signals. Each boosting stage has two branch charge pumps, wherein each branch charge pump at least has a main pass transistor, a pre-charge transistor, two substrate transistors and capacitors. The substrate transistors and the main pass transistor are operated in association with the four phase clock signals to keep a potential of the body of the main pass transistors at a low level thus mitigating the body effect.

Abstract: A charge pump circuit has an input stage, an output stage and multiple boosting stages coupled between the input stage and the output stage. The boosting stages are driven by four phase clock signals. Each boosting stage has two branch charge pumps, wherein each branch charge pump at least has a main pass transistor, a pre-charge transistor, two substrate transistors and capacitors. The substrate transistors and the main pass transistor are operated in association with the four phase clock signals to keep a potential of the body of the main pass transistors at a low level thus mitigating the body effect.