Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

Abstract: A button structure includes a switch, a shell, an elastic member, a button and at least one adjustable limiting member. The elastic member includes a fixing portion, a compressive portion and an elastic portion. The fixing portion is connected to the shell. The compressive portion is configured to abut against the switch. The elastic portion is connected between the fixing portion and the compressive portion. The elastic portion is suitable for deformation. The button is connected to the compressive portion, and the compressive portion is located between the button and the switch. The adjustable limiting member is disposed on the button, and is configured to abut against the elastic portion. The adjustable limiting member adjustably protrudes for a length toward the elastic portion relative to the button.

Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.

Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

Abstract: A display device includes a housing. The housing includes a main body, a first fixed end, a second fixed end, a third fixed end, a fourth fixed end, and an opening area. The opening area is disposed at a lower half portion of the main body. The opening area has a first opening, a second opening, and a third opening. The first opening has an axis extending along a first direction substantially perpendicular to a bottom side of the main body. The second opening is disposed on a first side of the first opening and has an axis extending along a second direction having a first angle with respect to the first direction. The third opening is disposed on a second side of the first opening opposite to the first side and has an axis along a third direction having a second angle with respect to the first direction.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.

Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A semiconductor device includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring. The at least one second dielectric layer is over the at least one first dielectric layer. The second conductive wiring is over the at least one second dielectric layer. The dielectric constant of the at least one second dielectric layer is higher than the dielectric constant of the at least one first dielectric layer.

Abstract: A block, and a backlight module and a display device using the block are provided. The block includes a capsule enclosing a cavity therein and a phase change material received in the cavity. The capsule is at least partially made of an elastic material. The phase change material has a melting point lower than the elastic material. The backlight module includes an optical film, a frame at least partially surrounding a side of the optical film, and the block disposed between the side of the optical film and the frame. The display device includes a display panel, a frame having an accommodation area for accommodating the display panel, and the block disposed between the display panel and the frame.

Abstract: A semiconductor device includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring. The at least one second dielectric layer is over the at least one first dielectric layer. The second conductive wiring is over the at least one second dielectric layer. The dielectric constant of the at least one second dielectric layer is higher than the dielectric constant of the at least one first dielectric layer.