Patents by Inventor Wu-Chang Tu
Wu-Chang Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8212347Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.Type: GrantFiled: June 30, 2010Date of Patent: July 3, 2012Assignees: ChipMOS Technologies Inc, ChipMOS Technologies (Bermuda) LtdInventors: Geng-Shin Shen, Wu-Chang Tu
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Patent number: 8207603Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.Type: GrantFiled: August 3, 2010Date of Patent: June 26, 2012Assignees: Chipmos Technologies Inc, Chipmos Technologies (Bermuda) LtdInventors: Geng-Shin Shen, Wu-Chang Tu
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Patent number: 8169061Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.Type: GrantFiled: June 30, 2010Date of Patent: May 1, 2012Assignees: Chipmos Technologies Inc, Chipmos Technologies (Bermuda) LtdInventors: Geng-Shin Shen, Wu-Chang Tu
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Patent number: 8026615Abstract: An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.Type: GrantFiled: June 29, 2010Date of Patent: September 27, 2011Assignee: Chipmos Technologies Inc.Inventors: Hung Tsun Lin, Wu Chang Tu, Cheng Ting Wu
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Publication number: 20100314729Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.Type: ApplicationFiled: August 3, 2010Publication date: December 16, 2010Inventors: Geng-Shin SHEN, Wu-Chang Tu
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Patent number: 7834432Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.Type: GrantFiled: June 8, 2009Date of Patent: November 16, 2010Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) LtdInventors: Wu-Chang Tu, Geng-Shin Shen
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Publication number: 20100264527Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Inventors: Geng-Shin SHEN, Wu-Chang Tu
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Publication number: 20100264530Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Inventors: Geng-Shin SHEN, Wu-Chang Tu
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Publication number: 20100264540Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: Hung Tsun Lin, Wu Chang Tu, Cheng Ting Wu
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Patent number: 7816771Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offset chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.Type: GrantFiled: July 16, 2007Date of Patent: October 19, 2010Assignees: Chipmos Technologies Inc., Chipmos Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, Wu-Chang Tu
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Patent number: 7786595Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.Type: GrantFiled: July 16, 2007Date of Patent: August 31, 2010Assignees: Chipmos Technologies Inc., Chipmos Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, Wu-Chang Tu
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Patent number: 7781898Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.Type: GrantFiled: May 29, 2007Date of Patent: August 24, 2010Assignee: Chipmos Technologies Inc.Inventors: Hung-Tsun Lin, Wu-Chang Tu, Cheng-Ting Wu
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Publication number: 20100006997Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.Type: ApplicationFiled: September 17, 2009Publication date: January 14, 2010Inventors: Geng-Shin SHEN, Wu-Chang Tu
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Patent number: 7615853Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.Type: GrantFiled: July 16, 2007Date of Patent: November 10, 2009Assignees: CHIPMOS Technologies Inc., CHIPMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, Wu-Chang Tu
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Publication number: 20090243056Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Applicants: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Wu-Chang Tu, Geng-Shin Shen
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Patent number: 7576416Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.Type: GrantFiled: February 10, 2006Date of Patent: August 18, 2009Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Wu-Chang Tu, Geng-Shin Shen
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Patent number: 7554197Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.Type: GrantFiled: April 10, 2006Date of Patent: June 30, 2009Assignees: ChipMOS Technologies (Bermuda) Ltd, ChipMOS Technologies Inc.Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee, Wu-Chang Tu, Chun-Hung Lin, Shih Feng Chiu
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Publication number: 20080174031Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.Type: ApplicationFiled: May 29, 2007Publication date: July 24, 2008Inventors: Hung-Tsun Lin, Wu-Chang Tu, Cheng-Ting Wu
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Publication number: 20080099896Abstract: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offset chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.Type: ApplicationFiled: July 16, 2007Publication date: May 1, 2008Inventors: Geng-Shin Shen, Wu-Chang Tu
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Publication number: 20080061412Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.Type: ApplicationFiled: July 16, 2007Publication date: March 13, 2008Inventors: Geng-Shin Shen, Wu-Chang Tu