Abstract: A single chip type white light LED device includes a first semiconductor layer of a first doping type, a ZnMnSeTe (Zinc Manganese Selenium Tellurium) red light quantum well, a first barrier layer disposed on the ZnMnSeTe red light quantum well, a green light emitting layer including green light quantum dots disposed on the first barrier layer, a second barrier layer disposed on the green light emitting layer, a blue light emitting layer including blue light quantum dots disposed on the second barrier layer, a third barrier layer disposed on the blue light emitting layer, and a second semiconductor layer disposed on the third barrier layer.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of4terial. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

Abstract: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1?x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1?x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

Abstract: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1-x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1-x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.