Patents by Inventor Wu Chou HSU

Wu Chou HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112848
    Abstract: A package structure is provided. The package structure includes an electronic component and a connection element. The electronic component includes a conductive wire and a magnetic layer encapsulating the conductive wire. The connection element penetrates and contacts the magnetic layer and the conductive wire.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hung Yi CHUANG
  • Patent number: 11784111
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Wu Chou Hsu
  • Publication number: 20220418115
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Publication number: 20220384309
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chin-Cheng KUO, Wu Chou HSU
  • Publication number: 20220285282
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Min-Yao CHEN
  • Patent number: 11432406
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
  • Patent number: 11342272
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Min-Yao Chen
  • Publication number: 20220157745
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Patent number: 11335650
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Publication number: 20220095462
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Patent number: 11239184
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Publication number: 20210391283
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Publication number: 20210391284
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Publication number: 20210391271
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Min-Yao CHEN