Patents by Inventor Wu-Chuan CHENG
Wu-Chuan CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230400997Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.Type: ApplicationFiled: August 25, 2023Publication date: December 14, 2023Applicant: Winbond Electronics Corp.Inventors: Wu-Chuan Cheng, Chien-Ti Hou
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Patent number: 11782622Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.Type: GrantFiled: January 25, 2022Date of Patent: October 10, 2023Assignee: Winbond Electronics Corp.Inventors: Wu-Chuan Cheng, Chien-Ti Hou
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Publication number: 20220236874Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.Type: ApplicationFiled: January 25, 2022Publication date: July 28, 2022Applicant: Winbond Electronics Corp.Inventors: Wu-Chuan Cheng, Chien-Ti Hou
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Patent number: 11315618Abstract: A memory operation method applicable to a memory storage device is provided. The memory operation method including the following steps: receiving, from a memory controller, a first operation command for performing a first memory operation on a memory array of the memory storage device; and in response to the first operation command, transmitting first address information of the memory array corresponding to the first memory operation to the memory controller through a data interface of the memory storage device. In addition, a memory storage device using the memory operation method is also provided.Type: GrantFiled: September 4, 2019Date of Patent: April 26, 2022Assignee: Winbond Electronics Corp.Inventors: Wu-Chuan Cheng, Chien-Ti Hou
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Patent number: 11188344Abstract: A memory apparatus and an operation method thereof are provided. The memory apparatus includes a mode configuration register, a system memory array, a pointer and an arithmetic circuit including logic operation units. The mode configuration register stores weight matrix information and a base address. The system memory array stores feature values in a feature map from the base address according to the weight matrix information. The pointer stores the base address and a weight matrix size to provide pointer information. The arithmetic circuit sequentially or parallelly reads the feature values according to the pointer information. The arithmetic circuit parallelly arranges weight coefficients of a selected weight matrix and the corresponding feature values in each of the corresponding logic operation units according to the weight matrix information, and causes the logic operation units to perform computing operations parallelly to output intermediate layer feature values to an external processing unit.Type: GrantFiled: February 1, 2021Date of Patent: November 30, 2021Assignee: Winbond Electronics Corp.Inventors: Chien-Ti Hou, Wu-Chuan Cheng
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Publication number: 20210240483Abstract: A memory apparatus and an operation method thereof are provided. The memory apparatus includes a mode configuration register, a system memory array, a pointer and an arithmetic circuit including logic operation units. The mode configuration register stores weight matrix information and a base address. The system memory array stores feature values in a feature map from the base address according to the weight matrix information. The pointer stores the base address and a weight matrix size to provide pointer information. The arithmetic circuit sequentially or parallelly reads the feature values according to the pointer information. The arithmetic circuit parallelly arranges weight coefficients of a selected weight matrix and the corresponding feature values in each of the corresponding logic operation units according to the weight matrix information, and causes the logic operation units to perform computing operations parallelly to output intermediate layer feature values to an external processing unit.Type: ApplicationFiled: February 1, 2021Publication date: August 5, 2021Applicant: Winbond Electronics Corp.Inventors: Chien-Ti Hou, Wu-Chuan Cheng
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Patent number: 10971212Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.Type: GrantFiled: March 6, 2020Date of Patent: April 6, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Chien-Ti Hou, Wu-Chuan Cheng
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Publication number: 20210065764Abstract: A memory operation method applicable to a memory storage device is provided. The memory operation method including the following steps: receiving, from a memory controller, a first operation command for performing a first memory operation on a memory array of the memory storage device; and in response to the first operation command, transmitting first address information of the memory array corresponding to the first memory operation to the memory controller through a data interface of the memory storage device. In addition, a memory storage device using the memory operation method is also provided.Type: ApplicationFiled: September 4, 2019Publication date: March 4, 2021Applicant: Winbond Electronics Corp.Inventors: Wu-Chuan Cheng, Chien-Ti Hou
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Publication number: 20200294572Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.Type: ApplicationFiled: March 6, 2020Publication date: September 17, 2020Applicant: Winbond Electronics Corp.Inventors: Chien-Ti HOU, Wu-Chuan CHENG