Abstract: Embodiments of a power stage with vertical integration for high-density, low-noise voltage regulators are described. In some embodiments, an Information Handling System (IHS) may include: a processor; and a multi-phase voltage regulator (VR) coupled to the processor, where the multi-phase VR comprises at least one power stage, and where the at least one power stage includes: a High-Side Field-Effect Transistor (HSFET) die mounted on a leadframe; a Low-Side FET (LSFET) die mounted on the leadframe; at least one decoupling capacitor mounted on the leadframe; and a driver circuit mounted on a clip, where the clip overlays at least a portion of the HSFET die and the LSFET die.