Abstract: A method and system of cell timing distribution which greatly reduces the bus bandwidth required for transmission of cell timing information in a WCDMA base station. The system of the present invention comprises a timing control unit connected to several communication cells through transmission lines. Each communication cell comprises a timing generator which determines a local timing (sfn) according to a frame boundary signal and a timing difference (t_cell) parameter received from the timing control unit. The frame boundary signal indicates the starting boundary of the central base station (nodeB) timing, whereas the t_cell parameter represents the offset between the local cell timing and the nodeB timing. The timing generator is implemented using a finite state machine and a counter.

Abstract: The present invention is related to a flexible distribution architecture and method for rake receiver of communication system, comprising: a plurality of processing units, further, each processing unit comprises: a plurality of rake receivers, wherein each rake receiver can receive a multi-path signal from its environment and, through a recovery process, outputs a recovered signal therefrom; an combiner, which connects with the plurality of rake receivers and receives a plurality of recovered signals, then further integrates the plural recovered signals which are originated from a same source by an integration process and, consequently, outputs an integrated signal therefrom; a master processing unit, which connects with the plural processing units and, through detecting the signal received, assigns an appropriate number of rake receivers to receive signals, and further the plural integrated signals originated from a same source are integrated by an integration process and, consequently, outputs a compound si

Abstract: A method and system for clock synchronization of semiconductor devices. The method uses a master-slave configuration to designate a semiconductor device with the lowest rate clock source as a master device and zero all clock sources inside the semiconductor device in order to output the zeroing lowest rate clock source to slave devices for clock synchronization of all clock sources respectively in the slave devices, and further implements a phase checker in each semiconductor device to ensure clock synchronization inside and between the semiconductor devices, so required clock signals are precisely provided to next internal circuits of the semiconductor devices.

Abstract: A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.

Abstract: A method and system of cell timing distribution which greatly reduces the bus bandwidth required for transmission of cell timing information in a WCDMA base station. The system of the present invention comprises a timing control unit connected to several communication cells through transmission lines. Each communication cell comprises a timing generator which determines a local timing (sfn) according to a frame boundary signal and a timing difference (t_cell) parameter received from the timing control unit. The frame boundary signal indicates the starting boundary of the central base station (nodeB) timing, whereas the t_cell parameter represents the offset between the local cell timing and the nodeB timing. The timing generator is implemented using a finite state machine and a counter.

Abstract: The present invention is related to a flexible distribution architecture and method for rake receiver of communication system, comprising: a plurality of processing units, further, each processing unit comprises: a plurality of rake receivers, wherein each rake receiver can receive a multi-path signal from its environment and, through a recovery process, outputs a recovered signal therefrom; an combiner, which connects with the plurality of rake receivers and receives a plurality of recovered signals, then further integrates the plural recovered signals which are originated from a same source by an integration process and, consequently, outputs an integrated signal therefrom; a master processing unit, which connects with the plural processing units and, through detecting the signal received, assigns an appropriate number of rake receivers to receive signals, and further the plural integrated signals originated from a same source are integrated by an integration process and, consequently, outputs a compound si

Abstract: A method and system for clock synchronization of semiconductor devices. The method uses a master-slave configuration to designate a semiconductor device with the lowest rate clock source as a master device and zero all clock sources inside the semiconductor device in order to output the zeroing lowest rate clock source to slave devices for clock synchronization of all clock sources respectively in the slave devices, and further implements a phase checker in each semiconductor device to ensure clock synchronization inside and between the semiconductor devices, so required clock signals are precisely provided to next internal circuits of the semiconductor devices.

Abstract: A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.

Abstract: There is disclosed a programmable memory emulator capable of emulating unspecified memory devices. A smart I/O interface is provided in the emulator for being programmed to conform to the interface specifications of different memory devices. An emulation look-ahead memory is employed to replace conventional two-port RAM. Furthermore, the memory of a host is utilized to emulate the functionality of system memory. Thus, the memory emulator is able to emulate various kinds of memory device, and the memory space is only restricted by the host.