Abstract: Electronic chips with slew-rate control at output signals are disclosed. A disclosed electronic chip includes a slew-rate control circuit and slew-rate control charging and discharging transistors wherein the transistors are coupled at an output pin of the electronic chip. According to an input signal for an output stage of the electronic chip and a signal at the output pin, the slew-rate control circuit generates the slew-rate control charging and discharging signals to separately control the slew-rate control charging and discharging transistors to charge/discharge a load capacitance at the output pin.

Abstract: A signal amplifying circuit is provided. The signal amplifying circuit includes a signal amplifier and a control circuit. The control circuit includes a compare unit and a register unit. The compare unit compares an input signal of the signal amplifier with a reference signal to generate a compare signal. The register unit receives and registers a control signal to be transmitted to the signal amplifier, and provides a registered signal to the signal amplifier according to the registered control signal when the compare signal is changed.

Abstract: An analog-to-digital converter with delta-sigma modulation and the modulation unit thereof are disclosed, wherein, for each modulation unit, a pair of input capacitors, a pair of integration capacitors and a differential feedback are operated in a swapping manner for the positive path and the negative path, such that circuit mismatch problems are effectively removed.

Abstract: Electronic chips with slew-rate control at output signals are disclosed. A disclosed electronic chip includes a slew-rate control circuit and slew-rate control charging and discharging transistors wherein the transistors are coupled at an output pin of the electronic chip. According to an input signal for an output stage of the electronic chip and a signal at the output pin, the slew-rate control circuit generates the slew-rate control charging and discharging signals to separately control the slew-rate control charging and discharging transistors to charge/discharge a load capacitance at the output pin.

Abstract: An analog-to-digital converter with delta-sigma modulation and the modulation unit thereof are disclosed, wherein, for each modulation unit, a pair of input capacitors, a pair of integration capacitors and a differential feedback are operated in a swapping manner for the positive path and the negative path, such that circuit mismatch problems are effectively removed.

Abstract: A signal amplifying circuit is provided. The signal amplifying circuit includes a signal amplifier and a control circuit. The control circuit includes a compare unit and a register unit. The compare unit compares an input signal of the signal amplifier with a reference signal to generate a compare signal. The register unit receives and registers a control signal to be transmitted to the signal amplifier, and provides a registered signal to the signal amplifier according to the registered control signal when the compare signal is changed.

Abstract: A variable gain amplifier, VGA, and related method are provided. A reference current variably controlled by a control signal is provided, then the reference current is divided to a load current and an input-control current according to differential driving between a constant reference signal and the control signal. Then the input-control current and the load current are used to respectively bias an input stage and an active load of the VGA, such that a gain of the VGA is controlled by a ratio between the input-control current and the load current. In this way, the gain can be controlled by the control signal. The VGA can provide wider gain range and better variable gain characteristics because a sum and a difference of the input-control current and the load current are both controlled by the control signal.

Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.

Abstract: A variable gain amplifier, VGA, and related method are provided. A reference current variably controlled by a control signal is provided, then the reference current is divided to a load current and an input-control current according to differential driving between a constant reference signal and the control signal. Then the input-control current and the load current are used to respectively bias an input stage and an active load of the VGA, such that a gain of the VGA is controlled by a ratio between the input-control current and the load current. In this way, the gain can be controlled by the control signal. The VGA can provide wider gain range and better variable gain characteristics because a sum and a difference of the input-control current and the load current are both controlled by the control signal.

Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.