Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.

Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.

Abstract: A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustment signal according to the number of the data stored in the FIFO buffer. The data stored in the FIFO buffer are sent out to an external device at a clock rate derived from a master clock signal. The control circuit provides a PLL adjustment signal according to the FIFO adjustment signal. The PLL provides the master clock signal and adjusts the frequency of the master clock signal in response to the PLL adjustment signal.

Abstract: A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustment signal according to the number of the data stored in the FIFO buffer. The data stored in the FIFO buffer are sent out to an external device at a clock rate derived from a master clock signal. The control circuit provides a PLL adjustment signal according to the FIFO adjustment signal. The PLL provides the master clock signal and adjusts the frequency of the master clock signal in response to the PLL adjustment signal.

Abstract: In a digital data link system which transmits and receives frequency-shift keyed digital data over mark/space frequency channels, the invention enhances system performance in the presence of noise. The method utilizes two synchronization channels, selecting the better one to synchronize the receiver to the transmitter. The method teaches the accumulation of the results of a plurality of data-state determining measurements and the utilization of the accumulated measurements made during a baud interval to resolve the received mark/space frequency signal into a corresponding mark/space data-state signal. Apparatus to practice the method is described. The apparatus includes a timing recovery circuit for synchronization-channel selection and a digital frequency detector capable of extracting information from a data signal in the presence of noise having the same frequency as the data signal and up to 86.6% of the amplitude of the data signal.