Abstract: Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle ? is formed between the long-side extension directions of the active regions and the first direction; wherein ? is a non-right angle.

Abstract: The present invention relates to nanofibers. In particular, the present invention relates to potassium niobate nanofibers. In an aspect of the present invention, there is provided a method of preparing the nanofibers, the method comprising: (a) dissolving niobium chloride and potassium sorbate in a solvent to obtain a first solution; (b) removing chloride precipitates formed from the first solution; (c) adding a polymer, for example polymethylmethacrylate or polyvinylpyrrolidone to the solution to obtain a second spinnable solution; and (d) electrospinning the spinnable solution to produce the fibers. The application also discloses the application of such nanofibers in the manufacture of a humidity sensor device by sputtering a metal such as Tantalum on top of the nanofibers.

Abstract: A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the first transistor extends in a substantially vertical direction. The channel of the second transistor extends in a substantially horizontal direction. A method for fabricating the semiconductor device is also disclosed.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

Abstract: A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the first transistor extends in a substantially vertical direction. The channel of the second transistor extends in a substantially horizontal direction. A method for fabricating the semiconductor device is also disclosed.

Abstract: A method includes etching a semiconductor substrate to form a recess, wherein the recess extends from a top surface of the semiconductor substrate into the semiconductor substrate. An enhanced cleaning is then performed to etch exposed portions of the semiconductor substrate. The exposed portions are in the recess. The enhanced cleaning is performed using process gases including hydrochloride (HCl) and germane (GeH4). After the enhanced cleaning, an epitaxy is performed to grow a semiconductor region in the recess.

Abstract: A method includes etching a semiconductor substrate to form a recess, wherein the recess extends from a top surface of the semiconductor substrate into the semiconductor substrate. An enhanced cleaning is then performed to etch exposed portions of the semiconductor substrate. The exposed portions are in the recess. The enhanced cleaning is performed using process gases including hydrochloride (HCl) and germane (GeH4). After the enhanced cleaning, an epitaxy is performed to grow a semiconductor region in the recess.

Abstract: A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

Abstract: A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

Abstract: A receptacle, which is adapted for nesting and stacking with similar receptacles. The invention, the receptacle is intended in particular to be utilized as a food pan for the receiving and storing of hot or cold food items, and, which may be employed in connection with buffet or steam tables, among other diverse uses thereof. The receptacle is preferably constituted of a metallic material, such as aluminum or stainless steel, which is compatible with food service requirements and sanitary prescriptions or regulations having a generally rectangular flat bottom, and wherein lower side and end walls extend upwardly in an outwardly angled slope from rounded edges connecting the receptacle bottom to the lower ends of the walls. At the upper ends of each of the side and end walls, these extend into outwardly and upwardly curved wall structures, which form a curvilinear ledge.

Abstract: A receptacle, which is adapted for nesting and stacking with similar receptacles. The invention, the receptacle is intended in particular to be utilized as a food pan for the receiving and storing of hot or cold food items, and, which may be employed in connection with buffet or steam tables, among other diverse uses thereof. The receptacle is preferably constituted of a metallic material, such as aluminum or stainless steel, which is compatible with food service requirements and sanitary prescriptions or regulations having a generally rectangular flat bottom, and wherein lower side and end walls extend upwardly in an outwardly angled slope from rounded edges connecting the receptacle bottom to the lower ends of the walls. At the upper ends of each of the side and end walls, these extend into outwardly and upwardly curved wall structures, which form a curvilinear ledge.

Abstract: The present invention discloses a method of improving an electroluminescent efficiency of a MOS device by etching a semiconductor substrate thereof. A chemical etching process is performed to remove surface states or surface defects located on the surface of a silicon substrate before a nanoparticle layer and a conducting layer is formed on the silicon substrate, in order that the non-radiative electron-hole recombination centers located on the surface of silicon substrate is suppressed. Accordingly, the percentage of radiative electron-hole recombination is heightened and the electroluminescent efficiency of a MOS light emitting device is drastically enhanced. Advantageously, the chemical etching step is able to create a nanostructure on the surface of the silicon substrate to increase the probability of the collision of electron-hole pairs and phonons, and the electroluminescent efficiency of a MOS light emitting device is improved as well.

Abstract: The present invention discloses a method of improving an electroluminescent efficiency of a MOS device by etching a semiconductor substrate thereof. A chemical etching process is performed to remove surface states or surface defects located on the surface of a silicon substrate before a nanoparticle layer and a conducting layer is formed on the silicon substrate, in order that the non-radiative electron-hole recombination centers located on the surface of silicon substrate is suppressed. Accordingly, the percentage of radiative electron-hole recombination is heightened and the electroluminescent efficiency of a MOS light emitting device is drastically enhanced. Advantageously, the chemical etching step is able to create a nanostructure on the surface of the silicon substrate to increase the probability of the collision of electron-hole pairs and phonons, and the electroluminescent efficiency of a MOS light emitting device is improved as well.

Abstract: A method of fabricating a planarized barrier cap layer over a metal structure comprising the following steps. A substrate having an opening formed therein is provided. The substrate having an upper surface. A planarized metal structure is formed within the opening. The planarized metal structure being substantially planar with the upper surface of the substrate. A portion of the planarized metal structure is removed using a reverse-electrochemical plating process to recess the metal structure from the upper surface of the substrate. A barrier cap layer is formed over the substrate and the recessed metal structure. The excess of the barrier cap layer is removed from over the substrate by a planarization process to form the planarized barrier cap layer over the metal structure.